Datasheet > 9DBL0951

9DBL0951

更新时间： 2023-12-20 18:44:06

品牌	Logo	应用领域
瑞萨 - RENESAS		PC
页数	文件大小	规格书
20页	572K
描述
9-Output 3.3V PCIe Fanout Clock Buffer

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9DBL0951 数据手册

9-Output 3.3V PCIe Fanout Buffer

9DBL09x1

DATASHEET

Description

Features/Benefits

The 9DBL09x1 devices are 3.3V members of IDT's

Full-Featured PCIe clock family. The 9DBL09x1 devices

support PCIe Gen1–4 Common Clocked (CC) and PCIe

Separate Reference Independent Spread (SRIS) systems.

They offer a choice of integrated output terminations

providing direct connection to 85Ω or 100Ω transmission

lines. The 9DBL09P1 can be factory programmed with a

user-defined power up default SMBus configuration.

• Direct connection to 100 (xx41) or 85 (xx51)

transmission lines; saves 36 resistors compared to

standard PCIe devices

• 165mW typical power consumption (at 3.3V); eliminates

thermal concerns

• VDDIO allows 50% power savings at optional 1.05V;

maximum power savings

• SMBus-selectable features allows optimization to customer

requirements:

Recommended Application

PCIe Gen1–4 clock distribution for Riser Cards, Storage,

Networking, JBOD, Communications, Access Points

– control input polarity

– control input pull up/downs

– slew rate for each output

– differential output amplitude

– output impedance for each output

Output Features

• 9 – 1-200 MHz Low-Power (LP) HCSL DIF pairs

• 9DBL0941 default Zout = 100Ω

• Customer defined SMBus power up default can be

programmed into P1 device; allows exact optimization to

customer requirements

• 9DBL0951 default Zout = 85Ω

• 9DBL09P1 factory programmable defaults

• OE# pins; support DIF power management

• HCSL differential input; can be driven by common clock

sources

• Easy AC-coupling to other logic families, see IDT

application note AN-891.

Key Specifications

• Spread spectrum tolerant; allows reduction of EMI

• DIF additive cycle-to-cycle jitter < 5ps

• DIF output-to-output skew < 50ps

• Additive phase jitter is 0ps (typical rms) for PCIe Gen1–4

CC, SRIS

• Device contains default configuration; SMBus interface not

required for device operation

• Three selectable SMBus addresses; multiple devices can

easily share an SMBus segment

• Space saving 48-pin 6 x 6mm VFQFPN; minimal board

space

• Additive phase jitter 111fs rms typical at 156.25M (1.5M to

10M)

Block Diagram

vOE(8:0)#

DIF8

DIF7

DIF6

DIF5

DIF4

DIF3

DIF2

DIF1

DIF0

CLK_IN

CLK_IN#

vSADR

^CKPWRGD_PD#

SDATA_3.3

SCLK_3.3

Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.

9DBL09x1 AUGUST 1, 2017

12 3 4 5 6 7...20

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