Datasheet > 935304545125

935304545125

更新时间： 2024-11-08 04:47:11

品牌	Logo	应用领域
恩智浦 - NXP		输入元件光电二极管逻辑集成电路
页数	文件大小	规格书
15页	106K
描述
IC GATE NOR 1CH 2INPUT 5TSSOP

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935304545125 数据手册

74AUP1G02-Q100

Low-power 2-input NOR gate

Rev. 1 — 4 June 2014

Product data sheet

1. General description

The 74AUP1G02-Q100 provides the single 2-input NOR function.

Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V_CCrange from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

V_CCrange from 0.8 V to 3.6 V.

This device is fully specified for partial Power-down applications using I_OFF

The I_OFFcircuitry disables the output, preventing the damaging backflow current through

the device when it is powered down.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

 Automotive product qualification in accordance with AEC-Q100 (Grade 1)

 Specified from 40 C to +85 C and from 40 C to +125 C

 Wide supply voltage range from 0.8 V to 3.6 V

 High noise immunity

 Complies with JEDEC standards:

 JESD8-12 (0.8 V to 1.3 V)

 JESD8-11 (0.9 V to 1.65 V)

 JESD8-7 (1.2 V to 1.95 V)

 JESD8-5 (1.8 V to 2.7 V)

 JESD8-B (2.7 V to 3.6 V)

 ESD protection:

 MIL-STD-883, method 3015 Class 3A. Exceeds 5000 V

 HBM JESD22-A114F Class 3A. Exceeds 5000 V

 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )

 Low static power consumption; I_CC= 0.9 A (maximum)

 Latch-up performance exceeds 100 mA per JESD 78 Class II

 Inputs accept voltages up to 3.6 V

 Low noise overshoot and undershoot < 10 % of V_CC

 I_OFFcircuitry provides partial Power-down mode operation

12 3 4 5 6 7...15

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