Datasheet > 91305AGT

91305AGT

更新时间： 2024-11-05 21:07:43

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
8页	89K
描述
Clock Driver

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中文翻译

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技术参数
数据手册

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91305AGT 技术参数

生命周期：	Obsolete	包装说明：	,
Reach Compliance Code：	unknown	风险等级：	5.84
Base Number Matches：	1

91305AGT 数据手册

ICS91305

Integrated

Circuit

Systems, Inc.

High Performance Communication Buffer

General Description

Features

The ICS91305 is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology

to align, in both phase and frequency, the REF input with

theCLKOUTsignal. Itisdesignedtodistributehighspeed

clocks in communication systems operating at speeds

from 10 to 133 MHz.

•

Zero input - output delay

Frequency range 10 - 133 MHz (3.3V)

5V tolerant input REF

High loop filter bandwidth ideal for Spread

Spectrum applications.

•

Less than 200 ps Jitter between outputs

Skew controlled outputs

Skew less than 250 ps between outputs

Available in 8 pin 150 mil SOIC & 173 mil

TSSOP packages

ICS91305 is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to

theinputofthePLL. Sincetheskewbetweentheinputand

outputislessthan+/-350pS, thepartactsasazerodelay

buffer.

•

3.3V 10ꢀ operation

The ICS91305 comes in an eight pin 150 mil SOIC

package. It has five output clocks. In the absence of REF

input, will be in the power down mode. In this mode, the

PLL is turned off and the output buffers are pulled low.

Powerdownmodeprovidesthelowestpowerconsumption

for a standby condition.

Block Diagram

Pin Configuration

REF

CLK2

CLK1

GND

CLKOUT

CLK4

VDD

CLK3

8 pin SOIC & TSSOP

0092H—12/02/08

12 3 4 5 6 7 8

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与91305AGT相关器件

型号	品牌	获取价格	描述	数据表
91305AM	IDT	获取价格	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150
91305AMI	IDT	获取价格	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150
91305AMILF	IDT	获取价格	HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay
91305AMILFT	IDT	获取价格	HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay
91305AMIT	IDT	获取价格	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150
91305AMT	IDT	获取价格	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150
91305MLF	IDT	获取价格	Clock Driver, PDSO8
91305YGILF-T	IDT	获取价格	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 4.40
91305YGI-T	IDT	获取价格	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 4.40
91305YGLFT	IDT	获取价格	PLL Based Clock Driver, 91305 Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 4.40