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91305AMILF PDF预览

91305AMILF

更新时间: 2024-11-05 12:28:15
品牌 Logo 应用领域
艾迪悌 - IDT 通信
页数 文件大小 规格书
9页 163K
描述
HIGH PERFORMANCE COMMUNICATION BUFFER Zero input - output delay

91305AMILF 数据手册

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DATASHEET  
HIGH PERFORMANCE COMMUNICATION BUFFER  
ICS91305I  
Description  
Features  
The ICS91305I is a high performance, low skew, low jitter  
clock driver. It uses a phase lock loop (PLL) technology to  
align, in both phase and frequency, the REF input with the  
CLKOUT signal. It is designed to distribute high speed  
clocks in communication systems operating at speeds from  
10 to 133 MHz.  
Zero input - output delay  
Frequency range 10 - 133 MHz (3.3V)  
5V tolerant input REF  
High loop filter bandwidth ideal for Spread Spectrum  
applications  
Less than 200 ps Jitter between outputs  
Skew controlled outputs  
ICS91305I is a zero delay buffer that provides  
synchronization between the input and output. The  
synchronization is established via CLKOUT feed back to the  
input of the PLL. Since the skew between the input and  
output is less than +/- 350 pS, the part acts as a zero delay  
buffer.  
Skew less than 250 ps between outputs  
Available in 8 pin 150 mil SOIC & 173 mil TSSOP  
packages  
3.3V 10% operation  
The ICS91305I comes in an eight pin 150 mil SOIC  
package. It has five output clocks. In the absence of REF  
input, will be in the power down mode. In this mode, the PLL  
is turned off and the output buffers are pulled low. Power  
down mode provides the lowest power consumption for a  
standby condition.  
Supports industrial temperature range -40°C to 85°C  
Block Diagram  
IDT® HIGH PERFORMANCE COMMUNICATION BUFFER  
1
ICS91305I  
REV G 090612  

91305AMILF 替代型号

型号 品牌 替代类型 描述 数据表
CY2305SXC-1HT CYPRESS

功能相似

Low-Cost 3.3V Zero Delay Buffer
CY2305SXC-1H CYPRESS

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Low-Cost 3.3V Zero Delay Buffer
CY2305CSXC-1 CYPRESS

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3.3V Zero Delay Clock Buffer

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