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91305YMLFT PDF预览

91305YMLFT

更新时间: 2024-02-01 18:45:59
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 89K
描述
PLL Based Clock Driver, 91305 Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 0.150 INCH, LEAD FREE, MS-012, SOIC-8

91305YMLFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SOP,针数:8
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83系列:91305
输入调节:STANDARDJESD-30 代码:R-PDSO-G8
JESD-609代码:e3长度:4.9 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER湿度敏感等级:1
功能数量:1反相输出次数:
端子数量:8实输出次数:5
最高工作温度:70 °C最低工作温度:
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
峰值回流温度(摄氏度):260认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.25 ns座面最大高度:1.75 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
温度等级:COMMERCIAL端子面层:Matte Tin (Sn)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:3.9 mm最小 fmax:133 MHz
Base Number Matches:1

91305YMLFT 数据手册

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ICS91305  
Integrated  
Circuit  
Systems, Inc.  
High Performance Communication Buffer  
General Description  
Features  
The ICS91305 is a high performance, low skew, low jitter  
clock driver. It uses a phase lock loop (PLL) technology  
to align, in both phase and frequency, the REF input with  
theCLKOUTsignal. Itisdesignedtodistributehighspeed  
clocks in communication systems operating at speeds  
from 10 to 133 MHz.  
Zero input - output delay  
Frequency range 10 - 133 MHz (3.3V)  
5V tolerant input REF  
High loop filter bandwidth ideal for Spread  
Spectrum applications.  
Less than 200 ps Jitter between outputs  
Skew controlled outputs  
Skew less than 250 ps between outputs  
Available in 8 pin 150 mil SOIC & 173 mil  
TSSOP packages  
ICS91305 is a zero delay buffer that provides  
synchronization between the input and output. The  
synchronization is established via CLKOUT feed back to  
theinputofthePLL. Sincetheskewbetweentheinputand  
outputislessthan+/-350pS, thepartactsasazerodelay  
buffer.  
3.3V 10ꢀ operation  
The ICS91305 comes in an eight pin 150 mil SOIC  
package. It has five output clocks. In the absence of REF  
input, will be in the power down mode. In this mode, the  
PLL is turned off and the output buffers are pulled low.  
Powerdownmodeprovidesthelowestpowerconsumption  
for a standby condition.  
Block Diagram  
Pin Configuration  
REF  
CLK2  
CLK1  
GND  
1
2
3
4
8
7
6
5
CLKOUT  
CLK4  
VDD  
CLK3  
8 pin SOIC & TSSOP  
0092H—12/02/08  

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