Datasheet > 91305MLF

91305MLF

更新时间： 2023-01-02 21:51:01

品牌	Logo	应用领域
艾迪悌 - IDT		光电二极管
页数	文件大小	规格书
7页	70K
描述
Clock Driver, PDSO8

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数据手册

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91305MLF 数据手册

ICS91305

Integrated

Circuit

Systems, Inc.

High Performance Communication Buffer

General Description

Features

The ICS91305 is a high performance, low skew, low jitter

clock driver. It uses a phase lock loop (PLL) technology

to align, in both phase and frequency, the REF input with

theCLKOUTsignal. Itisdesignedtodistributehighspeed

clocks in communication systems operating at speeds

from 10 to 133 MHz.

•

Zero input - output delay

Frequency range 10 - 133 MHz (3.3V)

5V tolerant input REF

High loop filter bandwidth ideal for Spread

Spectrum applications.

Less than 200 ps Jitter between outputs

Skew controlled outputs

Skew less than 250 ps between outputs

Available in 8 pin 150 mil SOIC & 173 mil

TSSOP packages

•

ICS91305 is a zero delay buffer that provides

synchronization between the input and output. The

synchronization is established via CLKOUT feed back to

theinputofthePLL. Sincetheskewbetweentheinputand

outputislessthan+/-350pS, thepartactsasazerodelay

buffer.

•

3.3V ±10% operation

The ICS91305 comes in an eight pin 150 mil SOIC

package. It has five output clocks. In the absence of REF

input, will be in the power down mode. In this mode, the

PLL is turned off and the output buffers are pulled low.

Powerdownmodeprovidesthelowestpowerconsumption

for a standby condition.

Block Diagram

Pin Configuration

REF

CLK2

CLK1

GND

CLKOUT

CLK4

VDD

CLK3

8 pin SOIC & TSSOP

0092F—08/20/04

12 3 4 5 6 7

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与91305MLF相关器件

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91305YGILF-T	IDT	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 4.40	获取价格
91305YGI-T	IDT	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 4.40	获取价格
91305YGLFT	IDT	PLL Based Clock Driver, 91305 Series, 5 True Output(s), 0 Inverted Output(s), PDSO8, 4.40	获取价格
91305YGT	IDT	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 4.40	获取价格
91305YMILF-T	IDT	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150	获取价格
91305YMI-T	IDT	PLL Based Clock Driver, 91305 Series, 4 True Output(s), 0 Inverted Output(s), PDSO8, 0.150	获取价格