85C82

更新时间： 2024-01-08 05:05:27

品牌	Logo	应用领域
美国微芯 - MICROCHIP		可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数	文件大小	规格书
8页	107K
描述
1K/2K/4K 5.0V CMOS Serial EEPROM

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中文翻译

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技术参数
数据手册

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85C82 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	0.207 INCH, PLASTIC, SOIC-8	针数：	8
Reach Compliance Code：	unknown	风险等级：	5.86
Is Samacsys：	N	其他特性：	10K ERASE/WRITE CYCLES MIN; DATA RETENTION > 40 YEARS
最大时钟频率 (fCLK)：	0.1 MHz	数据保留时间-最小值：	200
耐久性：	1000000 Write/Erase Cycles	I2C控制字节：	1010DDDR
JESD-30 代码：	R-PDSO-G8	JESD-609代码：	e0
长度：	5.28 mm	内存密度：	2048 bit
内存集成电路类型：	EEPROM	内存宽度：	8
功能数量：	1	端子数量：	8
字数：	256 words	字数代码：	256
工作模式：	SYNCHRONOUS	最高工作温度：	125 °C
最低工作温度：	-40 °C	组织：	256X8
输出特性：	OPEN-DRAIN	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP8,.3
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
并行/串行：	SERIAL	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
座面最大高度：	2.03 mm	串行总线类型：	I2C
最大待机电流：	0.0001 A	子类别：	EEPROMs
最大压摆率：	0.0045 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	AUTOMOTIVE	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	GULL WING	端子节距：	1.27 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	5.207 mm	最长写入周期时间 (tWC)：	1 ms
Base Number Matches：	1

85C82 数据手册

85C72/82/92

3.3

Stop Data Transfer (C)

2.0

FUNCTIONAL DESCRIPTION

The 85C72/82/92 supports a bidirectional two wire bus

and data transmission protocol. A device that sends

data onto the bus is deﬁned as transmitter, and a

device receiving data as receiver. The bus has to be

controlled by a master device which generates the

serial clock (SCL), controls the bus access, and gener-

ates the START and STOP conditions, while the

85C72/82/92 works as slave. Both, master and slave

can operate as transmitter or receiver, but the master

device determines which mode is activated.

A LOW to HIGH transition of the SDA line while the

clock (SCL) is HIGH determines a STOP condition. All

operations must be ended with a STOP condition.

3.4

Data Valid (D)

The state of the data line represents valid data when,

after a start condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Up to eight 85C72/82/92s can be connected to the bus,

selected by the A0, A1 and A2 chip address inputs.

Other devices can be connected to the bus, but require

different device codes than the 85C72/82/92 (refer to

section Slave Address).

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determined by the master device

and is theoretically unlimited.

3.0

BUS CHARACTERISTICS

The following bus protocol has been deﬁned:

3.5

Acknowledge

• Data transfer may be initiated only when the bus

is not busy.

Each receiving device, when addressed, is obliged to

generate an acknowledge after the reception of each

byte. The master device must generate an extra clock

pulse which is associated with this acknowledge bit.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in the data line while the clock line is HIGH will be

interpreted as a START or STOP condition.

Note: The 85C72/82/92 does not generate any

acknowledge bits if an internal program-

ming cycle is in progress.

Accordingly, the following bus conditions have been

deﬁned (see Figure 3-1).

The device that acknowledges, has to pull down the

SDA line during the acknowledge clock pulse in such a

way that the SDA line is stable LOW during the HIGH

period of the acknowledge related clock pulse. Of

course, setup and hold times must be taken into

account. A master must signal an end of data to the

slave by not generating an acknowledge bit on the last

byte that has been clocked out of the slave. In this

case the slave must leave the data line HIGH to enable

the master to generate the STOP condition

3.1

Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2

Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

clock (SCL) is HIGH determines a START condition.

All commands must be preceded by a START condi-

tion.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

(A)

(B)

(D)

(C)

(A)

SCL

SDA

START CONDITION

ADDRESS

ACKNOWLEDGE

VALID

DATA ALLOWED

TO CHANGE

STOP

CONDITION

DS11182C-page 4

1995 Microchip Technology Inc.

1 2 345 6 7 8

中文翻译

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与85C82相关器件

型号	品牌	获取价格	描述	数据表
85C82/J	ETC	获取价格	I2C Serial EEPROM
85C82/P	ETC	获取价格	I2C Serial EEPROM
85C82/S	MICROCHIP	获取价格	256 X 8 I2C/2-WIRE SERIAL EEPROM, UUC8
85C82/SM	ETC	获取价格	I2C Serial EEPROM
85C82/SN	ETC	获取价格	I2C Serial EEPROM
85C82/W	MICROCHIP	获取价格	256 X 8 I2C/2-WIRE SERIAL EEPROM, UUC8
85C82-E/J	ETC	获取价格	I2C Serial EEPROM
85C82E/P	MICROCHIP	获取价格	256 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, DIP-8
85C82-E/P	MICROCHIP	获取价格	256 X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8, 0.300 INCH, PLASTIC, DIP-8
85C82E/SM	MICROCHIP	获取价格	256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, 0.207 INCH, PLASTIC, SOIC-8

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