Datasheet > 854S01AKILF

854S01AKILF

更新时间： 2024-02-27 19:20:17

品牌	Logo	应用领域
艾迪悌 - IDT		逻辑集成电路
页数	文件大小	规格书
17页	300K
描述
2:1 Differential-to-LVDS Multiplexer

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854S01AKILF 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	VFQFPN
包装说明：	HVQCCN, LCC16,.12SQ,20	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	1.27
系列：	854	JESD-30 代码：	S-XQCC-N16
JESD-609代码：	e3	长度：	3 mm
逻辑集成电路类型：	MULTIPLEXER	湿度敏感等级：	3
功能数量：	1	输入次数：	2
输出次数：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出极性：	INVERTED	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC16,.12SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	3.3 V
Prop。Delay @ Nom-Sup：	0.6 ns	传播延迟（tpd）：	0.6 ns
认证状态：	Not Qualified	座面最大高度：	1 mm
子类别：	Clock Drivers	最大供电电压 (Vsup)：	3.465 V
最小供电电压 (Vsup)：	3.135 V	标称供电电压 (Vsup)：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Matte Tin (Sn) - annealed	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	3 mm
Base Number Matches：	1

854S01AKILF 数据手册

ICS854S01I Datasheet

2:1 DIFFERENTIAL-TO-LVDS MULTIPLEXER

VFQFN EPAD Thermal Release Path

In order to maximize both the removal of heat from the package and

the electrical performance, a land pattern must be incorporated on

the Printed Circuit Board (PCB) within the footprint of the package

corresponding to the exposed metal pad or exposed heat slug on the

package, as shown in Figure 4. The solderable area on the PCB, as

defined by the solder mask, should be at least the same size/shape

as the exposed pad/slug area on the package to maximize the

thermal/electrical performance. Sufficient clearance should be

designed on the PCB between the outer edges of the land pattern

and the inner edges of pad pattern for the leads to avoid any shorts.

and dependent upon the package power dissipation as well as

electrical conductivity requirements. Thus, thermal and electrical

analysis and/or testing are recommended to determine the minimum

number needed. Maximum thermal and electrical performance is

achieved when an array of vias is incorporated in the land pattern. It

is recommended to use as many vias connected to ground as

possible. It is also recommended that the via diameter should be 12

to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is

desirable to avoid any solder wicking inside the via during the

soldering process which may result in voids in solder between the

exposed pad/slug and the thermal land. Precautions should be taken

to eliminate any solder voids between the exposed heat slug and the

land pattern. Note: These recommendations are to be used as a

guideline only. For further information, please refer to the Application

Note on the Surface Mount Assembly of Amkor’s Thermally/

Electrically Enhance Leadframe Base Package, Amkor Technology.

While the land pattern on the PCB provides a means of heat transfer

and electrical grounding from the package to the board through a

solder joint, thermal vias are necessary to effectively conduct from

the surface of the PCB to the ground plane(s). The land pattern must

be connected to ground through these vias. The vias act as “heat

pipes”. The number of vias (i.e. “heat pipes”) are application specific

SOLDER

EXPOSED HEAT SLUG

PIN PAD

GROUND PLANE

LAND PATTERN

(GROUND PAD)

PIN PAD

THERMAL VIA

Figure 4. P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)

ICS854S01AKI June 15, 2017

1...8 9 101112 13 14...17

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与854S01AKILF相关器件

型号	品牌	描述	获取价格	数据表
854S01AKILFT	IDT	2:1 Differential-to-LVDS Multiplexer	获取价格
854S01I	RENESAS	2:1 Differential-to-LVDS Multiplexer	获取价格
854S054I	RENESAS	4:1 Differential-to-LVDS Clock Multiplexer	获取价格
854S057B_16	IDT	4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination	获取价格
854S057BGILF	IDT	4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination	获取价格
854S057BGILFT	IDT	4:1 or 2:1 LVDS Clock Multiplexer with Internal Input Termination	获取价格

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