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854S204BGILFT PDF预览

854S204BGILFT

更新时间: 2024-02-16 15:42:37
品牌 Logo 应用领域
艾迪悌 - IDT 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
23页 1425K
描述
Low Skew, Dual, Programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer

854S204BGILFT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP, TSSOP16,.25针数:16
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.8
系列:854输入调节:DIFFERENTIAL
JESD-30 代码:R-PDSO-G16JESD-609代码:e3
长度:5 mm逻辑集成电路类型:LOW SKEW CLOCK DRIVER
湿度敏感等级:1功能数量:2
反相输出次数:端子数量:16
实输出次数:2最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260电源:2.5/3.3 V
Prop。Delay @ Nom-Sup:0.5 ns传播延迟(tpd):0.5 ns
认证状态:Not QualifiedSame Edge Skew-Max(tskwd):0.015 ns
座面最大高度:1.2 mm子类别:Clock Drivers
最大供电电压 (Vsup):2.625 V最小供电电压 (Vsup):2.375 V
标称供电电压 (Vsup):2.5 V表面贴装:YES
温度等级:INDUSTRIAL端子面层:Matte Tin (Sn) - annealed
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:4.4 mmBase Number Matches:1

854S204BGILFT 数据手册

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Low Skew, Dual, Programmable 1-to-2  
Differential-to-LVDS, LVPECL Fanout Buffer  
ICS854S204I  
DATA SHEET  
General Description  
Features  
The ICS854S204I is a low skew, high performance dual,  
Two programmable differential LVDS or LVPECL output banks  
Two differential clock input pairs  
programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer.  
The PCLKx, nPCLKx pairs can accept most standard differential  
input levels. With the selection of SEL_OUT signal, outputs can be  
selected be to either LVDS or LVPECL levels. The ICS854S204I is  
characterized to operate from either a 2.5V or a 3.3V power supply.  
Guaranteed output and bank skew characteristics make the  
ICS854S204I ideal for those clock distribution applications  
demanding well defined performance and repeatability.  
PCLKx, nPCLKx pairs can accept the following differential  
input levels: LVDS, LVPECL, SSTL, CML  
Maximum output frequency: 3GHz  
Translates any single ended input signal to LVDS levels with  
resistor bias on nPCLKx inputs  
Output skew: 15ps (maximum)  
Bank skew: 15ps (maximum)  
Propagation delay: 500ps (maximum)  
Additive phase jitter, RMS: 0.15ps (typical)  
Full 3.3V or 2.5V supply modes  
Power Supply Configuration Table  
VDD = 3.3V  
3.3V Operation  
-40°C to 85°C ambient operating temperature  
Available in lead-free (RoHS 6) package  
VTAP = nc  
V
DD = 2.5V  
2.5V Operation  
VTAP = 2.5V  
SEL_OUT Function Table  
SEL_OUT  
Output Level  
LVDS  
LVPECL  
0
1
Block Diagram  
Pin Assignment  
VTAP  
PCLKA  
nPCLKA  
QA0  
1
2
3
4
5
6
7
8
16 nPCLKB  
PCLKB  
14 QB0  
Pulldown  
15  
SEL_OUT  
QA0  
nQA0  
Pulldown  
CLKA  
13  
12  
11  
10  
9
nQB0  
QB1  
nQA0  
QA1  
Pullup  
nCLKA  
QA1  
nQA1  
VTAP  
nQB1  
VDD  
nQA1  
GND  
SEL_OUT  
QB0  
nQB0  
Pulldown  
CLKB  
ICS854S204I  
Pullup  
nCLKB  
QB1  
16-Lead TSSOP  
4.4mm x 5.0mm x 0.925mm package body  
G Package  
nQB1  
Top View  
ICS854S204BGI REVISION B NOVEMBER 18, 2011  
1
©2011 Integrated Device Technology, Inc.  

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