Datasheet > 8430AY-71

8430AY-71

更新时间： 2024-01-26 18:19:15

品牌	Logo	应用领域
艾迪悌 - IDT		/
页数	文件大小	规格书
16页	210K
描述
Clock Generator, PQFP32

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技术参数
数据手册

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8430AY-71 技术参数

是否Rohs认证：	不符合	生命周期：	Active
Reach Compliance Code：	not_compliant	风险等级：	5.88
JESD-30 代码：	S-PQFP-G32	JESD-609代码：	e0
湿度敏感等级：	3	端子数量：	32
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	QFP
封装等效代码：	QFP32,.35SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	电源：	3.3 V
认证状态：	Not Qualified	子类别：	Clock Generators
标称供电电压：	3.3 V	表面贴装：	YES
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn85Pb15)
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	QUAD	Base Number Matches：	1

8430AY-71 数据手册

ICS8430-71

Integrated

Circuit

Systems, Inc.

700MH

Z, LOW

ITTER, CRYSTAL

NTERFACE

LVCMOS-TO-3.3V LVPECL FREQUENCY

SYNTHESIZER

POWER SUPPLY FILTERING TECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS8430-71 provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL.V_CC, V_CCA, and V_CCO

should be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required. Figure 4 illustrates how

a 10Ω resistor along with a 10µF and a .01µF bypass

capacitor should be connected to each V_CCApin.

3.3V

V_CC

.01µF

10Ω

V_CCA

10µF

FIGURE 4. POWER SUPPLY FILTERING

LAYOUT GUIDELINE

The schematic of the ICS8430-71 layout example used in this The layout in the actual system will depend on the selected

layout guideline is shown in Figure 5A. The ICS8430-71 rec- component types, the density of the components, the density

ommended PCB board layout for this example is shown in of the traces, and the stack up of the P.C. board.

Figure 5B.This layout example is used as a general guideline.

VCC

XTAL1

REF_IN

XTAL_SEL

TEST_CLK

nXTAL_SEL

VCCA

S_LOAD

S_DATA

S_CLOCK

VCCA

S_LOAD

S_DATA

S_CLOCK

C11

C16

10u

0.01u

VEE

ICS8430-71

VCC

125

Zo = 50 Ohm

IN+

C14

0.1u

TL1

C15

0.1u

Zo = 50 Ohm

IN-

TL2

FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT

www.icst.com/products/hiperclocks.html

8430AY-71

REV. B JANUARY 27, 2005

1...6 7 8910 11 12...16

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