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74VHC374TTR PDF预览

74VHC374TTR

更新时间: 2024-11-06 04:48:03
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 总线驱动器总线收发器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
14页 307K
描述
OCTAL D-TYPE FLIP FLOP WITH 3 STATE OUTPUTS NON INVERTING

74VHC374TTR 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:TSSOP
包装说明:TSSOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.17Is Samacsys:N
系列:AHC/VHCJESD-30 代码:R-PDSO-G20
JESD-609代码:e4长度:6.5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大频率@ Nom-Sup:100000000 Hz最大I(ol):0.008 A
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP20,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/5.5 V
Prop。Delay @ Nom-Sup:11.5 ns传播延迟(tpd):18.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:FF/Latches最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:NICKEL PALLADIUM GOLD
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
触发器类型:POSITIVE EDGE宽度:4.4 mm
Base Number Matches:1

74VHC374TTR 数据手册

 浏览型号74VHC374TTR的Datasheet PDF文件第2页浏览型号74VHC374TTR的Datasheet PDF文件第3页浏览型号74VHC374TTR的Datasheet PDF文件第4页浏览型号74VHC374TTR的Datasheet PDF文件第5页浏览型号74VHC374TTR的Datasheet PDF文件第6页浏览型号74VHC374TTR的Datasheet PDF文件第7页 
74VHC374  
OCTAL D-TYPE FLIP FLOP  
WITH 3 STATE OUTPUTS NON INVERTING  
HIGH SPEED:  
= 270 MHz (TYP.) at V = 5V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4 µA (MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28% V (MIN.)  
V
NIH  
NIL  
CC  
SOP  
TSSOP  
POWER DOWN PROTECTION ON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 8 mA (MIN)  
OH  
OL  
Table 1: Order Codes  
PACKAGE  
BALANCED PROPAGATION DELAYS:  
t
t
T & R  
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 5.5V  
SOP  
74VHC374MTR  
74VHC374TTR  
V
CC  
TSSOP  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 374  
While the (OE) input is low, the 8 outputs will be in  
a normal logic state (high or low logic level) and  
while high level the outputs will be in a high  
impedance state.  
IMPROVED LATCH-UP IMMUNITY  
LOW NOISE: V  
= 0.9V (MAX.)  
OLP  
DESCRIPTION  
The Output control does not affect the internal  
operation of flip flops; that is, the old data can be  
retained or the new data can be entered even  
while the outputs are off. Power down protection is  
provided on all inputs and 0 to 7V can be accepted  
on inputs with no regard to the supply voltage.  
This device can be used to interface 5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
The 74VHC374 is an advanced high-speed  
CMOS OCTAL D-TYPE FLIP FLOP with 3 STATE  
OUTPUTS NON INVERTING fabricated with  
sub-micron silicon gate and double-layer metal  
2
wiring C MOS technology.  
These 8 bit D-Type latch are controlled by a clock  
input (CK) and an output enable input (OE).  
On the positive transition of the clock, the Q  
outputs will be set to the logic state that were  
setup at the D inputs.  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 4  
1/14  
November 2004  

74VHC374TTR 替代型号

型号 品牌 替代类型 描述 数据表
74VHC374MTCX FAIRCHILD

类似代替

Octal D-Type Flip-Flop
74AHC374PW NXP

类似代替

Octal D-type flip-flop; positive edge-trigger; 3-state
74AHC374PW NEXPERIA

功能相似

Octal D-type flip-flop; positive-edge trigger; 3-stateProduction

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