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74VHC238T PDF预览

74VHC238T

更新时间: 2024-11-05 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 解码器
页数 文件大小 规格书
8页 67K
描述
3 TO 8 LINE DECODER

74VHC238T 数据手册

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74VHC238  
3 TO 8 LINE DECODER  
HIGH SPEED:tPD =5.5ns (TYP.) at VCC = 5V  
LOW POWER DISSIPATION:  
ICC =4 µA (MAX.) at TA =25 oC  
HIGH NOISEIMMUNITY:  
VNIH = VNIL =28% VCC (MIN.)  
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
M1  
T
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHC238M  
74VHC238T  
OPERATING VOLTAGERANGE:  
G2A or G2B is held high, decoding function is  
inhibited and all the 8 outputsgo to low.  
Three enable inputs are provided to ease  
cascade connection and application of this  
address decoders for memory systems.  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES238  
IMPROVED LATCH-UP IMMUNITY  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHC238 is an advanced high-speed  
CMOS 3 TO 8 LINE DECODER fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
If the device is enabled, 3 binary select inputs (A,  
B and C) determine which one of the outputs will  
go high. If enable input G1 is held low or either  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
June 1999  

74VHC238T 替代型号

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