74VHC238TTR

更新时间： 2024-11-04 04:48:03

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器
页数	文件大小	规格书
12页	313K
描述
3 TO 8 LINE DECODER

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中文翻译

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数据手册

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74VHC238TTR 数据手册

74VHC238

3 TO 8 LINE DECODER

■

HIGH SPEED: t = 5.5 ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 4 µA (MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

■

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

SOP

TSSOP

|I | = I = 8 mA (MIN)

■

BALANCED PROPAGATION DELAYS:

Table 1: Order Codes

PACKAGE

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

T & R

SOP

74VHC238MTR

74VHC238TTR

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 238

IMPROVED LATCH-UP IMMUNITY

TSSOP

Tree enable inputs are provided to ease cascade

connection and application of address decoders

for memory systems.

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

DESCRIPTION

The 74VHC238 is an advanced high-speed

CMOS 3 TO 8 LINE DECODER fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology.

If the device is enabled, 3 binary select inputs (A,

B, and C) determine which one of the outputs will

go high. If enable input G1 is held low or either

G2A or G2B is held high, decoding function is

inhibited and all the 8 outputs go to low.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 4

1/12

November 2004

12 3 4 5 6 7...12

中文翻译

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