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74VHC240 PDF预览

74VHC240

更新时间: 2024-11-03 22:48:39
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
8页 100K
描述
Octal Buffer/Line Driver with 3-STATE Outputs

74VHC240 数据手册

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October 1992  
Revised April 2005  
74VHC240  
Octal Buffer/Line Driver with 3-STATE Outputs  
General Description  
Features  
The VHC240 is an advanced high speed CMOS octal bus  
buffer fabricated with silicon gate CMOS technology. It  
achieves high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining the CMOS low power dissi-  
pation. The VHC240 is an inverting 3-STATE buffer having  
two active-LOW output enables. This device is designed to  
drive buslines or buffer memory address registers.  
High Speed: tPD 3.6ns (typ) at TA 25 C  
Low power dissipation: ICC  
4 A (max) @ TA 25 C  
High noise immunity: VNIH VNIL 28% VCC (min)  
Power down protection is provided on all inputs  
Low noise: VOLP 0.9V (max)  
Pin and function compatible with 74HC240  
An input protection circuit ensures that 0V to 7V can be  
applied to the input pins without regard to the supply volt-  
age. This device can be used to interface 5V to 3V systems  
and two supply systems such as battery backup. This cir-  
cuit prevents device destruction due to mismatched supply  
and input voltages.  
Ordering Code:  
Order Number Package Number  
Package Description  
74VHC240M  
74VHC240SJ  
74VHC240MTC  
74VHC240N  
M20B  
M20D  
MTC20  
N20A  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide  
Surface mount packages are also available on Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Pb-Free package per JEDEC J-STD-020B.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
© 2005 Fairchild Semiconductor Corporation  
DS011506  
www.fairchildsemi.com  

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