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74VHC126 PDF预览

74VHC126

更新时间: 2024-11-03 22:56:23
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
8页 64K
描述
QUAD BUS BUFFERS (3-STATE)

74VHC126 数据手册

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74VHC126  
QUAD BUS BUFFERS (3-STATE)  
PRELIMINARY DATA  
HIGH SPEED:tPD =3.8ns (TYP.) atVCC = 5V  
LOW POWER DISSIPATION:  
CC =4 µA (MAX.) at TA =25 oC  
I
HIGH NOISEIMMUNITY:  
M
T
VNIH = VNIL =28% VCC (MIN.)  
POWERDOWN PROTECTIONON INPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
|IOH| = IOL = 8 mA (MIN)  
BALANCEDPROPAGATIONDELAYS:  
tPLH tPHL  
(Micro Package)  
(TSSOPPackage)  
ORDER CODES :  
74VHC126M  
74VHC126T  
This device requires the 3-STATE control input G  
to be set low to place the output into the high  
impedance state.  
Power down protection is provided on all inputs  
and 0 to 7V can be accepted on inputs with no  
regard to the supply voltage. This device can be  
used to interface5V to 3V.  
OPERATING VOLTAGERANGE:  
VCC (OPR)= 2V to 5.5V  
PIN AND FUNCTION COMPATIBLEWITH  
74 SERIES126  
IMPROVED LATCH-UP IMMUNITY  
LOWNOISE:VOLP = 0.8V(Max.)  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
DESCRIPTION  
The 74VHC126 is an advanced high-speed  
CMOS QUAD BUS BUFFERS fabricated with  
sub-micron silicon gate and double-layer metal  
wiring C2MOS technology.  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
1/8  
June 1999  

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