Datasheet > 74VHC08_04

74VHC08_04

更新时间： 2024-11-04 04:48:03

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
11页	230K
描述
QUAD 2-INPUT AND GATE

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数据手册

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74VHC08_04 数据手册

74VHC08

QUAD 2-INPUT AND GATE

■

HIGH SPEED: t = 4.3 ns (TYP.) at V = 5V

PD CC

LOW POWER DISSIPATION:

= 2 µA (MAX.) at T =25°C

■

HIGH NOISE IMMUNITY:

= V = 28% V (MIN.)

NIH

NIL

■

POWER DOWN PROTECTION ON INPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

SOP

TSSOP

|I | = I = 8mA (MIN)

■

BALANCED PROPAGATION DELAYS:

Table 1: Order Codes

PACKAGE

PLH

PHL

OPERATING VOLTAGE RANGE:

(OPR) = 2V to 5.5V

T & R

SOP

74VHC08MTR

74VHC08TTR

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 08

TSSOP

■

IMPROVED LATCH-UP IMMUNITY

LOW NOISE: V

= 0.8V (MAX.)

Power down protection is provided on all inputs

and 0 to 7V can be accepted on inputs with no

regard to the supply voltage. This device can be

used to interface 5V to 3V.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

OLP

DESCRIPTION

The 74VHC08 is an advanced high-speed CMOS

QUAD 2-INPUT AND GATE fabricated with

sub-micron silicon gate and double-layer metal

wiring C MOS technology.

The internal circuit is composed of 2 stages

including buffer output, which provides high noise

immunity and stable output.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 5

1/11

November 2004

12 3 4 5 6 7...11

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