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74VCX162240_05 PDF预览

74VCX162240_05

更新时间: 2024-11-05 04:01:11
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 驱动器
页数 文件大小 规格书
8页 161K
描述
Low Voltage 16-Bit Inverting Buffer/Line Driver with 3.6V Tolerant Inputs and Outputs and 26ohm Series Resistors in Outputs

74VCX162240_05 数据手册

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January 1998  
Revised June 2005  
74VCX162240  
Low Voltage 16-Bit Inverting Buffer/Line Driver  
with 3.6V Tolerant Inputs and Outputs  
and 26: Series Resistors in Outputs  
General Description  
The VCX162240 contains sixteen inverting buffers with  
Features  
1.4V to 3.6V VCC supply operation  
3-STATE outputs to be employed as  
a memory and  
3.6V tolerant inputs and outputs  
26 series resistors in outputs  
tPD  
address driver, clock driver, or bus oriented transmitter/  
receiver. The device is nibble (4-bit) controlled. Each nibble  
has separate 3-STATE control inputs which can be shorted  
together for full 16-bit operation.  
3.3 ns max for 3.0V to 3.6V VCC  
The 74VCX162240 is designed for low voltage (1.4V to  
3.6V) VCC applications with I/O capability up to 3.6V. The  
Power-off high impedance inputs and outputs  
Supports live insertion and withdrawal (Note 1)  
74VCX162240 is also designed with 26 series resistors in  
the outputs. This design reduces line noise in applications  
such as memory address drivers, clock drivers, and bus  
transceivers/transmitters.  
Static Drive (IOH/IOL  
)
12 mA @ 3.0V VCC  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
The 74VCX162240 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model 2000V  
Machine model 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Order Number  
Package Number  
Package Descriptions  
74VCX162240MTD  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
I0I15  
Output Enable Input (Active LOW)  
Inputs  
O0O15  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS500091  
www.fairchildsemi.com  

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