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74VCX162373_05 PDF预览

74VCX162373_05

更新时间: 2024-11-24 04:47:59
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 锁存器
页数 文件大小 规格书
8页 153K
描述
Low Voltage 16-Bit Transparent Latch with 3.6V Tolerant Inputs and Outputs and 26ohm Series Resistors in Outputs

74VCX162373_05 数据手册

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January 2000  
Revised June 2005  
74VCX162373  
Low Voltage 16-Bit Transparent Latch  
with 3.6V Tolerant Inputs and Outputs  
and 26: Series Resistors in Outputs  
General Description  
The VCX162373 contains sixteen non-inverting latches  
with 3-STATE outputs and is intended for bus oriented  
Features  
1.4V–3.6V VCC supply operation  
3.6V tolerant inputs and outputs  
applications. The device is byte controlled. The flip-flops  
appear to be transparent to the data when the Latch enable  
(LE) is HIGH. When LE is LOW, the data that meets the  
setup time is latched. Data appears on the bus when the  
Output Enable (OE) is LOW. When OE is HIGH, the out-  
puts are in a high impedance state.  
26 series resistors in outputs  
tPD (In to On)  
3.3 ns max for 3.0V to 3.6V VCC  
The VCX162373 is also designed with 26 resistors in the  
outputs. This design reduces line noise in applications  
such as memory address drivers, clock drivers and bus  
transceivers/transmitters.  
Power-off high impedance inputs and outputs  
Support live insertion and withdrawal (Note 1)  
Static Drive (IOH/IOL  
)
12 mA @ 3.0V VCC  
The 74VCX162373 is designed for low voltage (1.4V to  
3.6V) VCC applications with I/O compatibility up to 3.6V.  
Uses patented noise/EMI reduction circuitry  
Latch-up performance exceeds 300 mA  
ESD performance:  
The 74VCX162373 is fabricated with an advanced CMOS  
technology to achieve high speed operation while maintain-  
ing low CMOS power dissipation.  
Human body model 2000V  
Machine model 200V  
Note 1: To ensure the high-impedance state during power up or power  
down, OE should be tied to V  
through a pull-up resistor; the minimum  
CC  
value of the resistor is determined by the current-sourcing capability of the  
driver.  
Ordering Code:  
Package  
Ordering Number  
Number  
Package Description  
74VCX162373MTD  
MTD48  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
Devices also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbol  
Pin Descriptions  
Pin Names  
Description  
OEn  
LEn  
Output Enable Input (Active LOW)  
Latch Enable Input  
Inputs  
I0I15  
O0O15  
Outputs  
© 2005 Fairchild Semiconductor Corporation  
DS500236  
www.fairchildsemi.com  

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