74VCX162373
Low-Voltage 1.8/2.5/3.3V
16-Bit Transparent Latch
With 26W Series Resisters and
3.6V–Tolerant Inputs and Outputs
(3–State, Non–Inverting)
http://onsemi.com
The 74VCX162373 is an advanced performance, non–inverting 16–bit
transparent latch. It is designed for very high–speed, very low–power
operation in 1.8 V, 2.5 V or 3.3 V systems. The VCX162373 is byte
controlled, with each byte functioning identically, but independently.
Each byte has separate Output Enable and Latch Enable inputs. These
control pins can be tied together for full 16–bit operation.
MARKING DIAGRAM
48
48
74VCX162373DT
AWLYYWW
When operating at 2.5 V (or 1.8 V) the part is designed to tolerate
voltages it may encounter on either inputs or outputs when interfacing to
3.3 V busses. It is guaranteed to be over–voltage tolerant to 3.6 V.
The 74VCX162373 contains 16 D–type latches with 3–state 3.6
V–tolerant outputs. It is designed with 26W series resistors in each of the
outputs to reduce noise. When the Latch Enable (LEn) inputs are HIGH,
data on the Dn inputs enters the latches. In this condition, the latches are
transparent, (a latch output will change state each time its D input
changes). When LE is LOW, the latch stores the information that was
present on the D inputs a setup time preceding the HIGH–to–LOW
transition of LE. The 3–state outputs are controlled by the Output Enable
(OEn) inputs. When OE is LOW, the outputs are enabled. When OE is
HIGH, the standard outputs are in the high impedance state, but this does
not interfere with new data entering into the latches.
1
TSSOP–48
DT SUFFIX
CASE 1201
1
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
• Designed for Low Voltage Operation: V = 1.65–3.6 V
• 3.6 V Tolerant Inputs and Outputs
• High Speed Operation: 3.3 ns max for 3.0 to 3.6 V
4.5 ns max for 2.3 to 2.7 V
CC
Device
Package
TSSOP
TSSOP
Shipping
39 / Rail
74VCX162373DT
74VCX162373DTR
2500 / Reel
9.0 ns max for 1.65 to 1.95 V
• Static Drive: ±12 mA Drive at 3.0 V
±8 mA Drive at 2.3 V
±3 mA Drive at 1.65 V
• Supports Live Insertion and Withdrawal
• I
Specification Guarantees High Impedance When V = 0 V
OFF
CC
• Near Zero Static Supply Current in All Three Logic States (20 µA)
Substantially Reduces System Power Requirements
• Latchup Performance Exceeds ±300 mA @ 125°C
• ESD Performance: Human Body Model >2000 V; Machine Model >200 V
Semiconductor Components Industries, LLC, 2000
1
Publication Order Number:
August, 2000 – Rev. 0
74VCX162373/D
This Material Copyrighted by Its Respective Manufacturer