January 1999
Revised June 2002
74LVT162245 • 74LVTH162245
Low Voltage 16-Bit Transceiver with 3-STATE Outputs
and 25Ω Series Resistors in A Port Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVT162245 and LVTH162245 contains sixteen non-
inverting bidirectional buffers with 3-STATE outputs and is
intended for bus oriented applications. The device is byte
controlled. Each byte has separate control inputs which
can be shorted together for full 16-bit operation. The T/R
inputs determine the direction of data flow through the
device. The OE inputs disable both the A and B ports by
placing them in a high impedance state.
5V VCC
■ Bushold data inputs eliminate the need for external pull-
up resistors to hold unused inputs (74LVTH162245),
also available without bushold feature (74LVT162245).
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
The LVT162245 and LVTH162245 are designed with
equivalent 25Ω series resistance in both the HIGH and
LOW states on the A Port outputs. This design reduces line
noise in applications such as memory address drivers,
clock drivers, and bus transceivers/transmitters.
■ A Port outputs include equivalent series resistance of
25Ω making external termination resistors unnecessary
and reducing overshoot and undershoot
■ A Port outputs source/sink ±12 mA.
B Port outputs source/sink −32 mA/+64 mA
The LVTH162245 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
■ Functionally compatible with the 74 series 162245
■ Latch-up performance exceeds 500 mA
■ ESD performance:
These non-inverting transceivers are designed for low volt-
age (3.3V) VCC applications, but with the capability to pro-
Human-body model > 2000V
vide a TTL interface to a 5V environment. The LVT162245
and LVTH162245 are fabricated with an advanced
BiCMOS technology to achieve high speed operation simi-
lar to 5V ABT while maintaining a low power dissipation.
Machine model > 200V
Charged-device model > 1000V
■ Also packaged in plastic Fine Pitch Ball Grid Array
(FBGA)
Ordering Code:
Order Number
Package Number
Package Description
74LVT162245G
(Note 1)(Note 2)
BGA54A
(Preliminary)
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162245MEA
(Note 2)
MS48A
MTD48
BGA54A
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide
74LVT162245MTD
(Note 2)
74LVTH162245G
(Note 1)(Note 2)
74LVTH162245MEA
74LVTH162245MEX
74LVTH162245MTD
74LVTH162245MTX
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TUBE]
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide
[TAPE and REEL]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBE]
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Ordering code “G” indicates Trays.
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
© 2002 Fairchild Semiconductor Corporation
DS012446
www.fairchildsemi.com