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74LVTH162245MTX

更新时间： 2024-11-04 22:56:23
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 总线驱动器总线收发器电阻器逻辑集成电路光电二极管信息通信管理
页数 文件大小 规格书
9页 99K
描述
Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25? Series Resistors in A Port Outputs

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74LVTH162245MTX 技术参数

是否Rohs认证：符合生命周期：Obsolete
零件包装代码：TSSOP包装说明：6.10 MM, MO-153, TSSOP-48
针数：48Reach Compliance Code：unknown
风险等级：7.17Is Samacsys：N
其他特性：WITH DIRECTION CONTROL控制类型：COMMON CONTROL
计数方向：BIDIRECTIONAL系列：LVT
JESD-30 代码：R-PDSO-G48JESD-609代码：e3
长度：12.5 mm逻辑集成电路类型：BUS TRANSCEIVER
最大I（ol）：0.064 A湿度敏感等级：2
位数：8功能数量：2
端口数量：2端子数量：48
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE WITH SERIES RESISTOR输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP48,.3,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：4 ns传播延迟（tpd）：4.6 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
翻译：N/A宽度：6.1 mm
Base Number Matches：1

74LVTH162245MTX 数据手册

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January 1999  
Revised June 2005  
74LVT162245 • 74LVTH162245  
Low Voltage 16-Bit Transceiver with 3-STATE Outputs  
and 25: Series Resistors in A Port Outputs  
General Description  
Features  
■ Input and output interface capability to systems at  
The LVT162245 and LVTH162245 contains sixteen non-  
inverting bidirectional buffers with 3-STATE outputs and is  
intended for bus oriented applications. The device is byte  
controlled. Each byte has separate control inputs which  
can be shorted together for full 16-bit operation. The T/R  
inputs determine the direction of data flow through the  
device. The OE inputs disable both the A and B ports by  
placing them in a high impedance state.  
5V VCC  
■ Bushold data inputs eliminate the need for external pull-  
up resistors to hold unused inputs (74LVTH162245),  
also available without bushold feature (74LVT162245).  
■ Live insertion/extraction permitted  
■ Power Up/Down high impedance provides glitch-free  
bus loading  
The LVT162245 and LVTH162245 are designed with  
equivalent 25 series resistance in both the HIGH and  
LOW states on the A Port outputs. This design reduces line  
noise in applications such as memory address drivers,  
clock drivers, and bus transceivers/transmitters.  
■ A Port outputs include equivalent series resistance of  
25 making external termination resistors unnecessary  
and reducing overshoot and undershoot  
■ A Port outputs source/sink 12 mA.  
B Port outputs source/sink 32 mA/ 64 mA  
The LVTH162245 data inputs include bushold, eliminating  
the need for external pull-up resistors to hold unused  
inputs.  
■ Functionally compatible with the 74 series 162245  
■ Latch-up performance exceeds 500 mA  
■ ESD performance:  
These non-inverting transceivers are designed for low volt-  
age (3.3V) VCC applications, but with the capability to pro-  
Human-body model 2000V  
vide a TTL interface to a 5V environment. The LVT162245  
and LVTH162245 are fabricated with an advanced  
BiCMOS technology to achieve high speed operation simi-  
lar to 5V ABT while maintaining a low power dissipation.  
Machine model 200V  
Charged-device model 1000V  
■ Also packaged in plastic Fine Pitch Ball Grid Array  
(FBGA)  
Ordering Code:  
Order Number  
Package Number  
Package Description  
74LVT162245G  
(Note 1)(Note 2)  
BGA54A  
(Preliminary)  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74LVT162245MEA  
(Note 2)  
MS48A  
MTD48  
BGA54A  
MS48A  
MS48A  
MTD48  
MTD48  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide  
74LVT162245MTD  
(Note 2)  
74LVTH162245G  
(Note 1)(Note 2)  
74LVTH162245MEA  
74LVTH162245MEX  
74LVTH162245MTD  
74LVTH162245MTX  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
[TUBE]  
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide  
[TAPE and REEL]  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[TUBE]  
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide  
[TAPE and REEL]  
Note 1: Ordering code “G” indicates Trays.  
Note 2: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
© 2005 Fairchild Semiconductor Corporation  
DS012446  
www.fairchildsemi.com  
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中文翻译

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74LVTH162245MTX 替代型号

型号 品牌 替代类型 描述 数据表
74LVTH162245MTD FAIRCHILD

完全替代

 Low Voltage 16-Bit Transceiver with 3-STATE Outputs and 25? Series Resistors in A Port Out
74LVTH162245DGGRG4 TI

类似代替

 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS
SN74LVTH162245DGGR TI

功能相似

 3.3-V ABT 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS

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74LVTH162245ZRDR TI

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