October 2000
Revised November 2000
74LVTH162373
Low Voltage 16-Bit Transparent Latch with
3-STATE Outputs and
25Ω Series Resistors in the Outputs
General Description
Features
■ Input and output interface capability to systems at
The LVTH162373 contains sixteen non-inverting latches
with 3-STATE outputs and is intended for bus oriented
applications. The device is byte controlled. The flip-flops
appear transparent to the data when the Latch Enable (LE)
is HIGH. When LE is LOW, the data that meets the setup
time is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH, the outputs are in
a high impedance state.
5V VCC
■ Bushold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
■ Live insertion/extraction permitted
■ Power Up/Down high impedance provides glitch-free
bus loading
■ Outputs include equivalent series resistance of 25Ω to
make external termination resistors unnecessary and
reduce overshoot and undershoot
The LVTH162373 is designed with equivalent 25Ω series
resistance in both the HIGH and LOW states of the output.
This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus transceiv-
ers/transmitters.
■ Functionally compatible with the 74 series 16373
■ Latch-up performance exceeds 500 mA
■ ESD performance:
The LVTH162373 data inputs include bushold, eliminating
the need for external pull-up resistors to hold unused
inputs.
Human-body model > 2000V
Machine model > 200V
These latches are designed for low-voltage (3.3V) VCC
Charged-device model > 1000V
applications, but with the capability to provide a TTL inter-
face to a 5V environment. The LVTH162373 is fabricated
with an advanced BiCMOS technology to achieve high
speed operation similar to 5V ABT while maintaining a low
power dissipation.
Ordering Code:
Package
Order Number
Package Description
Number
74LVTH162373MEA
MS48A
MS48A
MTD48
MTD48
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TUBES]
74LVTH162373MEX
(Note 1)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300 Wide
[TAPE and REEL]
74LVTH162373MTD
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TUBES]
74LVTH162373MTX
(Note 1)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
[TAPE and REEL]
Note 1: Use this Order Number to receive devices in Tape and Reel.
Logic Symbol
© 2000 Fairchild Semiconductor Corporation
DS500354
www.fairchildsemi.com