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74LVQ245SJX PDF预览

74LVQ245SJX

更新时间: 2024-11-20 20:24:03
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 光电二极管逻辑集成电路
页数 文件大小 规格书
6页 65K
描述
Bus Transceiver, LVQ Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 5.30 MM, EIAJ TYPE2, SOP-20

74LVQ245SJX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:5.30 MM, EIAJ TYPE2, SOP-20针数:20
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.26Is Samacsys:N
其他特性:WITH DIRECTION CONTROL控制类型:COMMON CONTROL
计数方向:BIDIRECTIONAL系列:LVQ
JESD-30 代码:R-PDSO-G20JESD-609代码:e3
长度:12.6 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS TRANSCEIVER最大I(ol):0.012 A
湿度敏感等级:1位数:8
功能数量:1端口数量:2
端子数量:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP20,.3
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):15 ns认证状态:Not Qualified
座面最大高度:2.1 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):2.7 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED翻译:N/A
宽度:5.3 mmBase Number Matches:1

74LVQ245SJX 数据手册

 浏览型号74LVQ245SJX的Datasheet PDF文件第2页浏览型号74LVQ245SJX的Datasheet PDF文件第3页浏览型号74LVQ245SJX的Datasheet PDF文件第4页浏览型号74LVQ245SJX的Datasheet PDF文件第5页浏览型号74LVQ245SJX的Datasheet PDF文件第6页 
February 1992  
Revised June 2001  
74LVQ245  
Low Voltage Octal Bidirectional Transceiver  
with 3-STATE Outputs  
General Description  
Features  
Ideal for low power/low noise 3.3V applications  
The LVQ245 contains eight non-inverting bidirectional buff-  
ers with 3-STATE outputs and is intended for bus-oriented  
applications. Current sinking capability is 12 mA at both the  
A and B ports. The Transmit/Receive (T/R) input deter-  
mines the direction of data flow through the bidirectional  
transceiver. Transmit (active-HIGH) enables data from A  
ports to B ports; Receive (active-LOW) enables data from  
B ports to A ports. The Output Enable input, when HIGH,  
disables both A and B ports by placing them in a HIGH Z  
condition.  
Implements patented EMI reduction circuitry  
Available in SOIC JEDEC, SOIC EIAJ and QSOP  
packages  
Guaranteed simultaneous switching noise level and  
dynamic threshold performance  
Improved latch-up immunity  
Guaranteed incident wave switching into 75  
4 kV minimum ESD immunity  
Ordering Code  
Order Number  
74LVQ245SC  
74LVQ245SJ  
Package Number  
M20B  
Package Description  
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide  
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide  
M20D  
74LVQ245QSC  
MQA20  
Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
Truth Table  
OE  
Output Enable Inputs  
T/R  
Transmit/Receive Input  
Side A Inputs or  
Inputs  
Outputs  
A0A7  
OE  
T/R  
L
3-STATE Outputs  
Side B Inputs or  
L
Bus B Data to Bus A  
Bus A Data to Bus B  
HIGH-Z State  
B0B7  
L
H
3-STATE Outputs  
H
X
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
© 2001 Fairchild Semiconductor Corporation  
DS011357  
www.fairchildsemi.com  

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