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74LVQ273MTR PDF预览

74LVQ273MTR

更新时间: 2024-11-18 04:47:51
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
13页 317K
描述
OCTAL D-TYPE FLIP FLOP WITH CLEAR

74LVQ273MTR 数据手册

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74LVQ273  
OCTAL D-TYPE FLIP FLOP WITH CLEAR  
HIGH SPEED:  
= 150 MHz (TYP.) at V = 3.3 V  
f
MAX  
CC  
COMPATIBLE WITH TTL OUTPUTS  
LOW POWER DISSIPATION:  
I
= 4 µA (MAX.) at T =25°C  
CC  
A
LOW NOISE:  
= 0.4V (TYP.) at V = 3.3V  
SOP  
TSSOP  
V
OLP  
CC  
75TRANSMISSION LINE DRIVING  
CAPABILITY  
Table 1: Order Codes  
PACKAGE  
SYMMETRICAL OUTPUT IMPEDANCE:  
T & R  
|I | = I = 12mA (MIN) at V = 3.0 V  
OH  
OL  
CC  
SOP  
74LVQ273MTR  
74LVQ273TTR  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
TSSOP  
t
t
PLH  
PHL  
2
wiring C MOS technology. It is ideal for low power  
and low noise 3.3V applications.  
OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 3.6V (1.2V Data Retention)  
V
CC  
Information signals applied to D inputs are  
transferred to the Q outputs on the positive going  
edge of the CLOCK pulse.  
When the CLEAR input is held low, the Q outputs  
are held low independently of the other inputs.  
All inputs and outputs are equipped with  
protection circuits against static discharge, giving  
them 2KV ESD immunity and transient excess  
voltage.  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 273  
IMPROVED LATCH-UP IMMUNITY  
DESCRIPTION  
The 74LVQ273 is a low voltage CMOS OCTAL  
D-TYPE FLIP FLOP WITH CLEAR fabricated with  
sub-micron silicon gate and double-layer metal  
Figure 1: Pin Connection And IEC Logic Symbols  
Rev. 5  
1/13  
July 2004  

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