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74LVC8T245PW,118 PDF预览

74LVC8T245PW,118

更新时间: 2024-09-09 15:26:39
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管逻辑集成电路
页数 文件大小 规格书
28页 208K
描述
74LVC(H)8T245 - 8-bit dual supply translating transceiver; 3-state TSSOP2 24-Pin

74LVC8T245PW,118 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:TSSOP2包装说明:TSSOP, TSSOP24,.25
针数:24Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:7.82
控制类型:COMMON CONTROL计数方向:BIDIRECTIONAL
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G24
JESD-609代码:e4长度:7.8 mm
负载电容(CL):15 pF逻辑集成电路类型:BUS TRANSCEIVER
最大I(ol):0.024 A湿度敏感等级:1
位数:8功能数量:1
端口数量:2端子数量:24
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP24,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:3.3 V
Prop。Delay @ Nom-Sup:10.3 ns传播延迟(tpd):32 ns
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.2 V标称供电电压 (Vsup):1.5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
翻译:1.8/5.5V &1.8/5.5V宽度:4.4 mm
Base Number Matches:1

74LVC8T245PW,118 数据手册

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74LVC8T245; 74LVCH8T245  
8-bit dual supply translating transceiver; 3-state  
Rev. 3 — 12 December 2011  
Product data sheet  
1. General description  
The 74LVC8T245; 74LVCH8T245 are 8-bit dual supply translating transceivers with  
3-state outputs that enable bidirectional level translation. They feature two data  
input-output ports (pins An and Bn), a direction control input (DIR), an output enable input  
(OE) and dual supply pins (VCC(A) and VCC(B)). Both VCC(A) and VCC(B) can be supplied at  
any voltage between 1.2 V and 5.5 V making the device suitable for translating between  
any of the low voltage nodes (1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Pins An, OE and  
DIR are referenced to VCC(A) and pins Bn are referenced to VCC(B). A HIGH on DIR allows  
transmission from An to Bn and a LOW on DIR allows transmission from Bn to An. The  
output enable input (OE) can be used to disable the outputs so the buses are effectively  
isolated.  
The devices are fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when either VCC(A) or VCC(B) are at  
GND level, both A port and B port are in the high-impedance OFF-state.  
Active bus hold circuitry in the 74LVCH8T245 holds unused or floating data inputs at a  
valid logic level.  
2. Features and benefits  
Wide supply voltage range:  
VCC(A): 1.2 V to 5.5 V  
VCC(B): 1.2 V to 5.5 V  
High noise immunity  
Complies with JEDEC standards:  
JESD8-7 (1.2 V to 1.95 V)  
JESD8-5 (1.8 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
HBM JESD22-A114F Class 3A exceeds 4000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Maximum data rates:  
420 Mbps (3.3 V to 5.0 V translation)  
210 Mbps (translate to 3.3 V))  
140 Mbps (translate to 2.5 V)  
75 Mbps (translate to 1.8 V)  
 
 

74LVC8T245PW,118 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC8T245QPWRQ1 TI

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