Datasheet > 74LVC8T595PW

74LVC8T595PW

更新时间： 2024-09-15 01:10:47

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
33页	348K
描述
Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state

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74LVC8T595PW 数据手册

74LVC8T595

Dual supply 8-bit serial-in/serial-out or parallel-out shift

Rev. 1 — 9 May 2017

Product data sheet

1 General description

The 74LVC8T595 is an 8-bit serial-in/serial or parallel-out shift register with a storage

Data is shifted on the positive-going transitions of the SHCP input. The data in the shift

input. If both clocks are connected together, the shift register is always one clock pulse

ahead of the storage register.

V_CC(A)and V_CC(B)can be supplied at any voltage between 1.1 V and 5.5 V making the

device suitable for translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V,

2.5 V, 3.3 V and 5.0 V). Pins MR, SHCP, STCP, OE, DS and Q7S are referenced to

V_CC(A)and pins Qn are referenced to V_CC(B)

The device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing any damaging backflow current through the

device when it is powered down. In suspend mode when V_CC(A)is at GND level, the Qn

outputs are in the high-impedance OFF-state.

2 Features and benefits

• Wide supply voltage range:

– V_CC(A): 1.1 V to 5.5 V

– V_CC(B): 1.1 V to 5.5 V

• High noise immunity

• Complies with JEDEC standards:

– JESD8-12A (1.1 V to 1.3 V)

– JESD8-11A (1.4 V to 1.6 V)

– JESD8-7 (1.65 V to 1.95 V)

– JESD8-5 (2.3 V to 2.7 V)

– JESD8C (3.0 V to 3.6 V)

– JESD12-6 (4.5 V to 5.5 V)

• ESD protection:

– HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4000V

– CDM JESD22-C101E exceeds 1000 V

• Suspend mode

• Latch-up performance exceeds 100 mA per JESD 78 Class II

• ±24 mA output drive (V_CC(A)= V_CC(B)= 3.0 V)

• Inputs accept voltages up to 5.5 V

• I_OFFcircuitry provides partial Power-down mode operation

• Multiple package options

• Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...33

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