5秒后页面跳转
捷配首页

Datasheet > 74LVC8T595PW
74LVC8T595PW PDF预览

74LVC8T595PW

更新时间： 2024-11-10 01:10:47
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
33页 348K
描述
Dual supply 8-bit serial-in/serial-out or parallel-out shift register; 3-state

阅读下载

中文翻译

获取价格

74LVC8T595PW 数据手册

 浏览型号74LVC8T595PW的Datasheet PDF文件第2页浏览型号74LVC8T595PW的Datasheet PDF文件第3页浏览型号74LVC8T595PW的Datasheet PDF文件第4页浏览型号74LVC8T595PW的Datasheet PDF文件第5页浏览型号74LVC8T595PW的Datasheet PDF文件第6页浏览型号74LVC8T595PW的Datasheet PDF文件第7页 
74LVC8T595  
Dual supply 8-bit serial-in/serial-out or parallel-out shift  
register; 3-state  
Rev. 1 — 9 May 2017  
Product data sheet  
1 General description  
The 74LVC8T595 is an 8-bit serial-in/serial or parallel-out shift register with a storage  
register and 3-state outputs. Both the shift and storage register have separate clocks.  
Data is shifted on the positive-going transitions of the SHCP input. The data in the shift  
register is transferred to the storage register on a positive-going transition of the STCP  
input. If both clocks are connected together, the shift register is always one clock pulse  
ahead of the storage register.  
VCC(A) and VCC(B) can be supplied at any voltage between 1.1 V and 5.5 V making the  
device suitable for translating between any of the voltage nodes (1.2 V, 1.5 V, 1.8 V,  
2.5 V, 3.3 V and 5.0 V). Pins MR, SHCP, STCP, OE, DS and Q7S are referenced to  
VCC(A) and pins Qn are referenced to VCC(B)  
.
The device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing any damaging backflow current through the  
device when it is powered down. In suspend mode when VCC(A) is at GND level, the Qn  
outputs are in the high-impedance OFF-state.  
2 Features and benefits  
• Wide supply voltage range:  
– VCC(A): 1.1 V to 5.5 V  
– VCC(B): 1.1 V to 5.5 V  
• High noise immunity  
• Complies with JEDEC standards:  
– JESD8-12A (1.1 V to 1.3 V)  
– JESD8-11A (1.4 V to 1.6 V)  
– JESD8-7 (1.65 V to 1.95 V)  
– JESD8-5 (2.3 V to 2.7 V)  
– JESD8C (3.0 V to 3.6 V)  
– JESD12-6 (4.5 V to 5.5 V)  
• ESD protection:  
– HBM ANSI/ESDA/JEDEC JS-001 Class 3A exceeds 4000V  
– CDM JESD22-C101E exceeds 1000 V  
• Suspend mode  
• Latch-up performance exceeds 100 mA per JESD 78 Class II  
• ±24 mA output drive (VCC(A) = VCC(B) = 3.0 V)  
• Inputs accept voltages up to 5.5 V  
• IOFF circuitry provides partial Power-down mode operation  
• Multiple package options  
• Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 
1234567...33

中文翻译

下载PDF

与74LVC8T595PW相关器件

型号 品牌 获取价格 描述 数据表
74LVCC3245ADBQRE4 TI

获取价格

 		OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
74LVCC3245ADBQRG4 TI

获取价格

 		OCTAL BUS TRANSCEIVER WITH ADJUSTABLE OUTPUT VOLTAGE AND 3-STATE OUTPUTS
74LVCC3245ASOG IDT

获取价格

 		SOIC-24, Tube
74LVCC3245ASOG8 IDT

获取价格

 		SOIC-24, Reel
74LVCE161284DGGRE4 TI

获取价格

 		19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
74LVCE161284DGGRG4 TI

获取价格

 		19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
74LVCE161284DLG4 TI

获取价格

 		19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
74LVCE161284DLRG4 TI

获取价格

 		19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
74LVCE161284VRE4 TI

获取价格

 		19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP
74LVCE161284VRG4 TI

获取价格

 		19-BIT IEEE STD 1284 TRANSLATION TRANSCEIVER WITH ERROR-FREE POWER UP

与74LVC8T595PW相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证