Datasheet > 74LVC3G06GT-G

74LVC3G06GT-G

更新时间： 2024-09-28 15:26:39

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
21页	279K
描述
Triple inverter with open-drain output

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74LVC3G06GT-G 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.75
Base Number Matches：	1

74LVC3G06GT-G 数据手册

74LVC3G06

Triple inverter with open-drain output

Rev. 11 — 28 March 2013

Product data sheet

1. General description

The 74LVC3G06 provides three inverting buffers.

The output of this device is an open drain and can be connected to other open-drain

outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

This device is fully specified for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits

 Wide supply voltage range from 1.65 V to 5.5 V

 5 V tolerant input/output for interfacing with 5 V logic

 High noise immunity

 Complies with JEDEC standard:

 JESD8-7 (1.65 V to 1.95 V)

 JESD8-5 (2.3 V to 2.7 V)

 JESD8-B/JESD36 (2.7 V to 3.6 V)

 ESD protection:

 HBM JESD22-A114F exceeds 2000 V

 MM JESD22-A115-A exceeds 200 V

 24 mA output drive (V_CC= 3.0 V)

 CMOS low power consumption

 Latch-up performance exceeds 250 mA

 Direct interface with TTL levels

 Inputs accept voltages up to 5 V

 Multiple package options

 Specified from 40 C to +85 C and 40 C to +125 C

12 3 4 5 6 7...21

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