5秒后页面跳转
74LVC3G07GM PDF预览

74LVC3G07GM

更新时间: 2024-09-30 06:31:55
品牌 Logo 应用领域
恩智浦 - NXP 逻辑集成电路
页数 文件大小 规格书
16页 95K
描述
Triple buffer with open-drain output

74LVC3G07GM 技术参数

是否Rohs认证: 符合生命周期:Transferred
零件包装代码:QFN包装说明:1.60 X 1.60 MM, 0.50 MM HEIGHT, 0.50 MM PITCH, PLASTIC, MO-255, SOT902-1, QFN-8
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.4
系列:LVC/LCX/ZJESD-30 代码:S-PQCC-N8
长度:1.6 mm负载电容(CL):50 pF
逻辑集成电路类型:BUFFER最大I(ol):0.024 A
湿度敏感等级:1功能数量:3
输入次数:1端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:OPEN-DRAIN封装主体材料:PLASTIC/EPOXY
封装代码:HVQCCN封装等效代码:LCC8,.06SQ,20
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
包装方法:TAPE AND REEL峰值回流温度(摄氏度):260
电源:3.3 VProp。Delay @ Nom-Sup:4.7 ns
传播延迟(tpd):8.4 ns认证状态:Not Qualified
施密特触发器:NO座面最大高度:0.5 mm
子类别:Gates最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:30宽度:1.6 mm
Base Number Matches:1

74LVC3G07GM 数据手册

 浏览型号74LVC3G07GM的Datasheet PDF文件第2页浏览型号74LVC3G07GM的Datasheet PDF文件第3页浏览型号74LVC3G07GM的Datasheet PDF文件第4页浏览型号74LVC3G07GM的Datasheet PDF文件第5页浏览型号74LVC3G07GM的Datasheet PDF文件第6页浏览型号74LVC3G07GM的Datasheet PDF文件第7页 
74LVC3G07  
Triple buffer with open-drain output  
Rev. 06 — 16 June 2008  
Product data sheet  
1. General description  
The 74LVC3G07 provides three non-inverting buffers.  
The output of the device is an open-drain and can be connected to other open-drain  
outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.  
Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this  
device in a mixed 3.3 V and 5 V environment.  
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall  
time.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
2. Features  
I Wide supply voltage range from 1.65 V to 5.5 V  
I 5 V tolerant input/output for interfacing with 5 V logic  
I High noise immunity  
I Complies with JEDEC standard:  
N JESD8-7 (1.65 V to 1.95 V)  
N JESD8-5 (2.3 V to 2.7 V)  
N JESD8-B/JESD36 (2.7 V to 3.6 V).  
I ESD protection:  
N HBM JESD22-A114E exceeds 2000 V  
N MM JESD22-A115-A exceeds 200 V  
I 24 mA output drive (VCC = 3.0 V)  
I CMOS low power consumption  
I Latch-up performance exceeds 250 mA  
I Direct interface with TTL levels  
I Inputs accept voltages up to 5 V  
I Multiple package options  
I Specified from 40 °C to +85 °C and 40 °C to +125 °C.  

与74LVC3G07GM相关器件

型号 品牌 获取价格 描述 数据表
74LVC3G07GM,115 NXP

获取价格

74LVC3G07 - Triple buffer with open-drain output QFN 8-Pin
74LVC3G07GM,125 NXP

获取价格

74LVC3G07 - Triple buffer with open-drain output QFN 8-Pin
74LVC3G07GN NEXPERIA

获取价格

Triple buffer with open-drain outputProduction
74LVC3G07GS NEXPERIA

获取价格

Triple buffer with open-drain outputProduction
74LVC3G07GT NXP

获取价格

Triple buffer with open-drain output
74LVC3G07GT NEXPERIA

获取价格

Triple buffer with open-drain outputProduction
74LVC3G14 NXP

获取价格

Triple inverting Schmitt trigger with 5 V tolerant input
74LVC3G14 DIODES

获取价格

Triple gate 1 Input Schmitt Trigger Inverter
74LVC3G14_08 NXP

获取价格

Triple inverting Schmitt trigger with 5 V tolerant input
74LVC3G14DC NXP

获取价格

Triple inverting Schmitt trigger with 5 V tolerant input