Datasheet > 逻辑 > 栅极> 74LVC3G07DC

74LVC3G07DC

更新时间： 2024-02-02 17:10:17

品牌	Logo	应用领域
恩智浦 - NXP		栅极逻辑集成电路光电二极管
页数	文件大小	规格书
14页	79K
描述
Triple buffer with open-drain output

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技术参数
数据手册

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74LVC3G07DC 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.73
Base Number Matches：	1

74LVC3G07DC 数据手册

74LVC3G07

Triple buffer with open-drain output

Rev. 03 — 01 February 2005

Product data sheet

1. General description

The 74LVC3G07 is a high-performance, low-power, low-voltage, Si-gate CMOS device

and superior to most advanced CMOS compatible TTL families.

Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

This device is fully speciﬁed for partial power-down applications using I_off. The I_offcircuitry

disables the output, preventing the damaging backﬂow current through the device when it

is powered down.

The 74LVC3G07 provides three non-inverting buffers.

The output of the device is an open drain and can be connected to other open-drain

outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

2. Features

■ Wide supply voltage range from 1.65 V to 5.5 V

■ 5 V tolerant input/output for interfacing with 5 V logic

■ High noise immunity

■ Complies with JEDEC standard:

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V).

■ ESD protection:

◆ HBM EIA/JESD22-A114-B exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V.

■ −24 mA output drive (V_CC= 3.0 V)

■ CMOS low power consumption

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...14

中文翻译

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