Datasheet > 逻辑 > 栅极> 74LVC3G07DP-G

74LVC3G07DP-G

更新时间： 2024-02-24 02:24:37

品牌	Logo	应用领域
恩智浦 - NXP		/
页数	文件大小	规格书
16页	95K
描述
Triple buffer with open-drain output - Description: Triple Buffer With Open-Drain Outputs ; Logic switching levels: TTL ; Number of pins: 8 ; Output drive capability: 32 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 2.1@3.3V ns; Voltage: 1.65 - 5.5

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

74LVC3G07DP-G 技术参数

Source Url Status Check Date：	2013-06-14 00:00:00	是否无铅：	含铅
是否Rohs认证：	符合	生命周期：	Active
Reach Compliance Code：	unknown	风险等级：	5.73
Base Number Matches：	1

74LVC3G07DP-G 数据手册

74LVC3G07

Triple buffer with open-drain output

Rev. 06 — 16 June 2008

Product data sheet

1. General description

The 74LVC3G07 provides three non-inverting buffers.

The output of the device is an open-drain and can be connected to other open-drain

outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.

Input can be driven from either 3.3 V or 5 V devices. This feature allows the use of this

device in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall

time.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant input/output for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8-B/JESD36 (2.7 V to 3.6 V).

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I −24 mA output drive (V_CC= 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Inputs accept voltages up to 5 V

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...16

中文翻译

下载PDF

与74LVC3G07DP-G相关器件

型号	品牌	获取价格	描述	数据表
74LVC3G07DP-Q100	NXP	获取价格	LVC/LCX/Z SERIES, TRIPLE 1-INPUT NON-INVERT GATE, PDSO8, 3 MM, PLASTIC, SOT505-2, TSSOP-8
74LVC3G07DP-Q100	NEXPERIA	获取价格	Triple buffer with open-drain outputProduction
74LVC3G07DP-Q100,125	NXP	获取价格	Buffer, LVC/LCX/Z Series, 3-Func, 1-Input, CMOS, PDSO8
74LVC3G07GD	NXP	获取价格	Triple buffer with open-drain output
74LVC3G07GM	NXP	获取价格	Triple buffer with open-drain output
74LVC3G07GM,115	NXP	获取价格	74LVC3G07 - Triple buffer with open-drain output QFN 8-Pin
74LVC3G07GM,125	NXP	获取价格	74LVC3G07 - Triple buffer with open-drain output QFN 8-Pin
74LVC3G07GN	NEXPERIA	获取价格	Triple buffer with open-drain outputProduction
74LVC3G07GS	NEXPERIA	获取价格	Triple buffer with open-drain outputProduction
74LVC3G07GT	NXP	获取价格	Triple buffer with open-drain output