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74LVC3G04_08

更新时间： 2024-01-24 20:07:41

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74LVC3G04_08 数据手册

74LVC3G04

Triple inverter

Rev. 07 — 16 June 2008

Product data sheet

1. General description

The 74LVC3G04 provides three inverting buffers.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing a damaging backﬂow current through the device

when it is powered down.

2. Features

I Wide supply voltage range from 1.65 V to 5.5 V

I 5 V tolerant outputs for interfacing with 5 V logic

I High noise immunity

I Complies with JEDEC standard:

N JESD8-7 (1.65 V to 1.95 V)

N JESD8-5 (2.3 V to 2.7 V)

N JESD8B/JESD36 (2.7 V to 3.6 V)

I ESD protection:

N HBM JESD22-A114E exceeds 2000 V

N MM JESD22-A115-A exceeds 200 V

I ±24 mA output drive (V_CC= 3.0 V)

I CMOS low power consumption

I Latch-up performance exceeds 250 mA

I Direct interface with TTL levels

I Multiple package options

I Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...16

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