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74LVC2G125DCURG4 PDF预览

74LVC2G125DCURG4

更新时间： 2024-01-28 23:05:25
品牌 Logo 应用领域
德州仪器 - TI 输出元件
页数 文件大小 规格书
14页 528K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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74LVC2G125DCURG4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：SOIC
包装说明：VSSOP, TSSOP8,.12,20针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：0.92
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：2.3 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.032 A湿度敏感等级：1
位数：1功能数量：2
端口数量：2端子数量：8
最高工作温度：125 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VSSOP
封装等效代码：TSSOP8,.12,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：0.01 mAProp。Delay @ Nom-Sup：4.3 ns
传播延迟（tpd）：9.1 ns认证状态：Not Qualified
座面最大高度：0.9 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：1.65 V
标称供电电压 (Vsup)：1.8 V表面贴装：YES
技术：CMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：2 mm
Base Number Matches：1

74LVC2G125DCURG4 数据手册

 浏览型号74LVC2G125DCURG4的Datasheet PDF文件第2页浏览型号74LVC2G125DCURG4的Datasheet PDF文件第3页浏览型号74LVC2G125DCURG4的Datasheet PDF文件第4页浏览型号74LVC2G125DCURG4的Datasheet PDF文件第5页浏览型号74LVC2G125DCURG4的Datasheet PDF文件第6页浏览型号74LVC2G125DCURG4的Datasheet PDF文件第7页 
SN74LVC2G125  
DUAL BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES204M–APRIL 1999–REVISED JANUARY 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.3 ns at 3.3 V  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2Y  
2A  
1Y  
VCC  
2OE  
1Y  
1
2
3
4
8
7
6
5
1OE  
1A  
VCC  
2OE  
1Y  
1
2
3
4
8
7
6
5
1OE  
1A  
3 6  
2 7  
1 8  
1A  
2OE  
VCC  
2Y  
1OE  
GND  
2A  
2Y  
GND  
2A  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
The SN74LVC2G125 is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features  
dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is  
high.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,  
preventing damaging current backflow through the device when it is powered down.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SSOP – DCT  
Reel of 3000  
SN74LVC2G125YZPR  
_ _ _CM_  
C25_ _ _  
Reel of 3000  
Reel of 3000  
Reel of 250  
SN74LVC2G125DCTR  
SN74LVC2G125DCUR  
SN74LVC2G125DCUT  
–40°C to 85°C  
VSSOP – DCU  
C25_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...14

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74LVC2G125DCURG4 替代型号

型号 品牌 替代类型 描述 数据表
74LVC2G125DCTRE6 TI

完全替代

 DUAL BUS BUFFER GATE WITH 3 STATE OUTPUTS
74LVC2G125DCTRE4 TI

完全替代

 DUAL BUS BUFFER GATE WITH 3 STATE OUTPUTS
74LVC2G125DCUTE4 TI

完全替代

 DUAL BUS BUFFER GATE WITH 3 STATE OUTPUTS

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