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74LVC2G125GD-G PDF预览

74LVC2G125GD-G

更新时间: 2024-02-05 20:45:56
品牌 Logo 应用领域
恩智浦 - NXP 驱动器
页数 文件大小 规格书
16页 92K
描述
IC,BUFFER/DRIVER,SINGLE,2-BIT,LCX/LVC-CMOS,LLCC,8PIN,PLASTIC

74LVC2G125GD-G 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VSON,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.23
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-N8
JESD-609代码:e3长度:1.95 mm
逻辑集成电路类型:BUS DRIVER湿度敏感等级:1
位数:1功能数量:2
端口数量:2端子数量:8
最高工作温度:125 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:VSON
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, VERY THIN PROFILE
峰值回流温度(摄氏度):260传播延迟(tpd):11.4 ns
认证状态:Not Qualified座面最大高度:0.5 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.65 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:1 mm
Base Number Matches:1

74LVC2G125GD-G 数据手册

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74LVC2G125  
Dual bus buffer/line driver; 3-state  
Rev. 08 — 7 September 2007  
Product data sheet  
1. General description  
The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.  
The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin  
nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at  
all inputs makes the circuit highly tolerant of slower input rise and fall times.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these  
devices as translators in a mixed 3.3 V and 5 V environment.  
This device is fully specified for partial power-down applications using IOFF. The IOFF  
circuitry disables the output, preventing the damaging backflow current through the device  
when it is powered down.  
2. Features  
Wide supply voltage range from 1.65 V to 5.5 V  
5 V tolerant input/output for interfacing with 5 V logic  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM EIA/JESD22-A114E exceeds 2000 V  
MM EIA/JESD22-A115-A exceeds 200 V  
±24 mA output drive (VCC = 3.0 V)  
CMOS low-power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
Specified from 40 °C to +85 °C and 40 °C to +125 °C  

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