74LVC2G125DP-G

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74LVC2G125DP-G 数据手册

74LVC2G125

Dual bus buffer/line driver; 3-state

Rev. 08 — 7 September 2007

Product data sheet

1. General description

The 74LVC2G125 provides a dual non-inverting buffer/line driver with 3-state output.

The 3-state output is controlled by the output enable input (pin nOE). A HIGH-level at pin

nOE causes the output to assume a high-impedance OFF-state. Schmitt trigger action at

all inputs makes the circuit highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

devices as translators in a mixed 3.3 V and 5 V environment.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

2. Features

■ Wide supply voltage range from 1.65 V to 5.5 V

■ 5 V tolerant input/output for interfacing with 5 V logic

■ High noise immunity

■ Complies with JEDEC standard:

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V)

■ ESD protection:

◆ HBM EIA/JESD22-A114E exceeds 2000 V

◆ MM EIA/JESD22-A115-A exceeds 200 V

■ ±24 mA output drive (V_CC= 3.0 V)

■ CMOS low-power consumption

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C

12 3 4 5 6 7...16

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74LVC2G125DP-Q100	NXP	获取价格	IC DRIVER, Bus Driver/Transceiver
74LVC2G125DP-Q100	NEXPERIA	获取价格	Dual bus buffer/line driver; 3-state
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74LVC2G125GF	NXP	获取价格	Dual bus buffer/line driver; 3-state
74LVC2G125GM	NXP	获取价格	Dual bus buffer/line driver 3-state
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74LVC2G125GN	NEXPERIA	获取价格	Dual bus buffer/line driver; 3-stateProduction
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