Datasheet > 74LVC2G125-Q100

74LVC2G125-Q100

更新时间： 2024-12-01 01:22:43

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
12页	215K
描述
Dual bus buffer/line driver; 3-state

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数据手册

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74LVC2G125-Q100 数据手册

74LVC2G125-Q100

Dual bus buffer/line driver; 3-state

Rev. 3 — 10 September 2018

Product data sheet

1. General description

The 74LVC2G125-Q100 provides a dual non-inverting buffer/line driver with 3-state output. The

output enable input (pin nOE) controls the 3-state output. A HIGH-level at pin nOE causes the

output to assume a high-impedance OFF-state. Schmitt trigger action at all inputs makes the circuit

highly tolerant of slower input rise and fall times.

Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices

as translators in a mixed 3.3 V and 5 V environment.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing a damaging backflow current through the device when it is powered

down.

This product has been qualified to the Automotive Electronics Council (AEC) standard Q100

(Grade 1) and is suitable for use in automotive applications.

2. Features and benefits

•

Automotive product qualification in accordance with AEC-Q100 (Grade 1)

Specified from -40 °C to +85 °C and from -40 °C to +125 °C

•

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant input/output for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

•

ESD protection:

•

MIL-STD-883, method 3015 exceeds 2000 V

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 Ω)

•

±24 mA output drive (V_CC= 3.0 V)

CMOS low-power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

3. Ordering information

Table 1. Ordering information

Type number

Package

Temperature range Name

Description

Version

74LVC2G125DP-Q100 -40 °C to +125 °C

TSSOP8

plastic thin shrink small outline package; 8 leads; SOT505-2

body width 3 mm; lead length 0.5 mm

74LVC2G125DC-Q100 -40 °C to +125 °C

VSSOP8

plastic very thin shrink small outline package;

8 leads; body width 2.3 mm

SOT765-1

12 3 4 5 6 7...12

中文翻译

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与74LVC2G125-Q100相关器件

型号	品牌	获取价格	描述	数据表
74LVC2G125RA3-7	DIODES	获取价格	DUAL BUFFER GATE WITH 3-STATE OUTPUTS
74LVC2G126	NXP	获取价格	Dual bus buffer/line driver; 3-state
74LVC2G126	DIODES	获取价格	Dual 3-State Buffer OE LOW
74LVC2G126_08	NXP	获取价格	Dual bus buffer/line driver; 3-state
74LVC2G126DC	NXP	获取价格	Dual bus buffer/line driver; 3-state
74LVC2G126DC	PHILIPS	获取价格	Bus Driver, 1-Func, 2-Bit, True Output, CMOS, PDSO8
74LVC2G126DC	NEXPERIA	获取价格	Dual bus buffer/line driver; 3-stateProduction
74LVC2G126DC,125	NXP	获取价格	74LVC2G126 - Dual bus buffer/line driver; 3-state SSOP 8-Pin
74LVC2G126DC-Q100	NEXPERIA	获取价格	Bus buffer/line driver; 3-state
74LVC2G126DCTRE4	TI	获取价格	DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

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