5秒后页面跳转
捷配首页

Datasheet > 逻辑 > 总线驱动器/收发器> 74LVC2G126DCURE4
74LVC2G126DCURE4 PDF预览

74LVC2G126DCURE4

更新时间： 2024-11-23 12:34:47
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
15页 824K
描述
DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

阅读下载

中文翻译

获取价格

74LVC2G126DCURE4 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：SOIC
包装说明：VSSOP, TSSOP8,.12,20针数：8
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.12控制类型：ENABLE HIGH
系列：LVC/LCX/ZJESD-30 代码：R-PDSO-G8
JESD-609代码：e4长度：2.3 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.024 A湿度敏感等级：1
位数：1功能数量：2
端口数量：2端子数量：8
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：VSSOP
封装等效代码：TSSOP8,.12,20封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, VERY THIN PROFILE, SHRINK PITCH包装方法：TAPE AND REEL
峰值回流温度（摄氏度）：260电源：3.3 V
Prop。Delay @ Nom-Sup：4 ns传播延迟（tpd）：9.8 ns
认证状态：Not Qualified座面最大高度：0.9 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：1.65 V标称供电电压 (Vsup)：1.8 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：2 mmBase Number Matches：1

74LVC2G126DCURE4 数据手册

 浏览型号74LVC2G126DCURE4的Datasheet PDF文件第2页浏览型号74LVC2G126DCURE4的Datasheet PDF文件第3页浏览型号74LVC2G126DCURE4的Datasheet PDF文件第4页浏览型号74LVC2G126DCURE4的Datasheet PDF文件第5页浏览型号74LVC2G126DCURE4的Datasheet PDF文件第6页浏览型号74LVC2G126DCURE4的Datasheet PDF文件第7页 
SN74LVC2G126  
DUAL BUS BUFFER GATE  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES205J–APRIL 1999–REVISED JANUARY 2007  
FEATURES  
•
Available in the Texas Instruments  
NanoFree™ Package  
•
•
•
Ioff Supports Partial-Power-Down Mode  
Operation  
•
•
•
•
•
•
Supports 5-V VCC Operation  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4 ns at 3.3 V  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
ESD Protection Exceeds JESD 22  
–
–
–
2000-V Human-Body Model (A114-A)  
200-V Machine Model (A115-A)  
Low Power Consumption, 10-µA Max ICC  
±24-mA Output Drive at 3.3 V  
1000-V Charged-Device Model (C101)  
Typical VOLP (Output Ground Bounce)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
•
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
DCT PACKAGE  
(TOP VIEW)  
DCU PACKAGE  
(TOP VIEW)  
YZP PACKAGE  
(BOTTOM VIEW)  
4 5  
GND  
2Y  
2A  
1Y  
VCC  
2OE  
1Y  
1
2
3
4
8
7
6
5
1OE  
1A  
VCC  
2OE  
1Y  
1
2
3
4
8
7
6
5
1OE  
1A  
3 6  
2 7  
1 8  
1A  
2OE  
VCC  
2Y  
1OE  
GND  
2A  
2Y  
GND  
2A  
See mechanical drawings for dimensions.  
DESCRIPTION/ORDERING INFORMATION  
This dual bus buffer gate is designed for 1.65-V to 5.5-V VCC operation.  
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the  
package.  
The SN74LVC2G126 is a dual bus driver/line driver with 3-state outputs. The outputs are disabled when the  
associated output-enable (OE) input is low.  
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a  
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the  
driver.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER TOP-SIDE MARKING(2)  
NanoFree™ – WCSP (DSBGA)  
0.23-mm Large Bump – YZP (Pb-free)  
SSOP – DCT  
Reel of 3000  
SN74LVC2G126YZPR  
_ _ _CN_  
C26_ _ _  
Reel of 3000  
Reel of 3000  
Reel of 250  
SN74LVC2G126DCTR  
SN74LVC2G126DCUR  
SN74LVC2G126DCUT  
–40°C to 85°C  
VSSOP – DCU  
C26_  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.  
DCU: The actual top-side marking has one additional character that designates the assembly/test site.  
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following  
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoFree is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1999–2007, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
1234567...15

中文翻译

下载PDF

74LVC2G126DCURE4 替代型号

型号 品牌 替代类型 描述 数据表
74LVC2G126DCUTG4 TI

完全替代

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SN74LVC2G126DCUR TI

完全替代

 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS

与74LVC2G126DCURE4相关器件

型号 品牌 获取价格 描述 数据表
74LVC2G126DCURG4 TI

获取价格

 		DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
74LVC2G126DCUTE4 TI

获取价格

 		DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
74LVC2G126DCUTG4 TI

获取价格

 		DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
74LVC2G126DP NXP

获取价格

 		Dual bus buffer/line driver; 3-state
74LVC2G126DP PHILIPS

获取价格

 		Bus Driver, 1-Func, 2-Bit, True Output, CMOS, PDSO8
74LVC2G126DP NEXPERIA

获取价格

 		Dual bus buffer/line driver; 3-stateProduction
74LVC2G126DP,125 NXP

获取价格

 		74LVC2G126 - Dual bus buffer/line driver; 3-state TSSOP 8-Pin
74LVC2G126DP/G NXP

获取价格

 		74LVC2G126DP/G
74LVC2G126DP-Q100 NXP

获取价格

 		LVC/LCX/Z SERIES, DUAL 1-BIT DRIVER, TRUE OUTPUT, PDSO8
74LVC2G126DP-Q100 NEXPERIA

获取价格

 		Bus buffer/line driver; 3-state

与74LVC2G126DCURE4相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证