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74LVC2G125DP PDF预览

74LVC2G125DP

更新时间: 2024-09-26 11:11:11
品牌 Logo 应用领域
安世 - NEXPERIA /
页数 文件大小 规格书
17页 268K
描述
Dual bus buffer/line driver; 3-stateProduction

74LVC2G125DP 数据手册

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74LVC2G125  
Dual bus buffer/line driver; 3-state  
Rev. 17 — 26 July 2021  
Product data sheet  
1. General description  
The 74LVC2G125 is a dual buffer/line driver with 3-state outputs controlled by the output enable  
inputs (nOE). Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of  
these devices as translators in mixed 3.3 V and 5 V environments.  
Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.  
This device is fully specified for partial power down applications using IOFF. The IOFF circuitry  
disables the output, preventing the potentially damaging backflow current through the device when  
it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
IOFF circuitry provides partial Power-down mode operation  
±24 mA output drive (VCC = 3.0 V)  
CMOS low-power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Overvoltage tolerant inputs to 5.5 V  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

74LVC2G125DP 替代型号

型号 品牌 替代类型 描述 数据表
74LVC2G125DP,125 NXP

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