Datasheet > 74LVC1G10GW

74LVC1G10GW

更新时间： 2024-11-21 11:11:07

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
15页	234K
描述
Single 3-input NAND gateProduction

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74LVC1G10GW 数据手册

74LVC1G10

Single 3-input NAND gate

Rev. 7 — 2 February 2022

Product data sheet

1. General description

The 74LVC1G10 provides a low-power, low-voltage single 3-input NAND gate.

The inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of this device

in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall time.

This device is fully specified for partial power-down applications using I_OFF. The I_OFFcircuitry

disables the output, preventing the damaging backflow current through the device when it is

powered down.

2. Features and benefits

•

Wide supply voltage range from 1.65 V to 5.5 V

•

High noise immunity

±24 mA output drive (V_CC= 3.0 V)

CMOS low power dissipation

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

I_OFFcircuitry provides partial Power-down mode operation

Complies with JEDEC standard:

•

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8C (2.7 V to 3.6 V)

JESD36 (4.5 V to 5.5 V)

•

ESD protection:

•

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

CDM JESD22-C101E exceeds 1000 V

•

Multiple package options

Specified from -40 °C to +85 °C and -40 °C to +125 °C

12 3 4 5 6 7...15

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