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74LVC1G00GW,165 PDF预览

74LVC1G00GW,165

更新时间: 2024-09-17 08:53:03
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
19页 346K
描述
74LVC1G00 - Single 2-input NAND-gate TSSOP 5-Pin

74LVC1G00GW,165 数据手册

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74LVC1G00  
Single 2-input NAND gate  
Rev. 10 — 2 July 2012  
Product data sheet  
1. General description  
The 74LVC1G00 provides the single 2-input NAND function.  
Input can be driven from either 3.3 V or 5 V devices. These features allow the use of  
these devices in a mixed 3.3 V and 5 V environment.  
Schmitt trigger action at all inputs makes the circuit tolerant for slower input rise and fall  
time.  
This device is fully specified for partial power-down applications using IOFF  
.
The IOFF circuitry disables the output, preventing the damaging backflow current through  
the device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
High noise immunity  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8-B/JESD36 (2.7 V to 3.6 V)  
24 mA output drive (VCC = 3.0 V)  
CMOS low power consumption  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Multiple package options  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Specified from 40 C to +85 C and 40 C to +125 C  

74LVC1G00GW,165 替代型号

型号 品牌 替代类型 描述 数据表
74LVC1G00GW,125 NXP

类似代替

74LVC1G00 - Single 2-input NAND-gate TSSOP 5-Pin

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