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74LVC1G02GM PDF预览

74LVC1G02GM

更新时间: 2024-09-17 11:12:35
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
16页 251K
描述
Single 2-input NOR gateProduction

74LVC1G02GM 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VSON,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.26
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-N6
JESD-609代码:e3长度:1.45 mm
逻辑集成电路类型:NOR GATE湿度敏感等级:1
功能数量:1输入次数:2
端子数量:6最高工作温度:125 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:VSON封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, VERY THIN PROFILE峰值回流温度(摄氏度):260
传播延迟(tpd):10.5 ns认证状态:Not Qualified
座面最大高度:0.5 mm最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):1.65 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Tin (Sn)
端子形式:NO LEAD端子节距:0.5 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
宽度:1 mmBase Number Matches:1

74LVC1G02GM 数据手册

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74LVC1G02  
Single 2-input NOR gate  
Rev. 15 — 8 February 2022  
Product data sheet  
1. General description  
The 74LVC1G02 is a single 2-input NOR gate. Inputs can be driven from either 3.3 V or 5 V  
devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V  
environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and  
fall times. This device is fully specified for partial power down applications using IOFF. The IOFF  
circuitry disables the output, preventing the potentially damaging backflow current through the  
device when it is powered down.  
2. Features and benefits  
Wide supply voltage range from 1.65 V to 5.5 V  
Overvoltage tolerant inputs to 5.5 V  
High noise immunity  
CMOS low power dissipation  
IOFF circuitry provides partial Power-down mode operation  
±24 mA output drive (VCC = 3.0 V)  
Latch-up performance exceeds 250 mA  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7 (1.65 V to 1.95 V)  
JESD8-5 (2.3 V to 2.7 V)  
JESD8C (2.7 V to 3.6 V)  
JESD36 (4.5 V to 5.5 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V  
Multiple package options  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
 
 

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