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74LVC1G04GF

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74LVC1G04GF 数据手册

74LVC1G04

Single inverter

Rev. 07 — 27 August 2007

Product data sheet

1. General description

The 74LVC1G04 provides one inverting buffer.

Input can be driven from either 3.3 V or 5 V devices. These features allow the use of these

devices in a mixed 3.3 V and 5 V environment.

Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall

time.

This device is fully speciﬁed for partial power-down applications using I_OFF. The I_OFF

circuitry disables the output, preventing the damaging backﬂow current through the device

when it is powered down.

2. Features

■ Wide supply voltage range from 1.65 V to 5.5 V

■ 5 V tolerant inputs for interfacing with 5 V logic

■ High noise immunity

■ Complies with JEDEC standard:

◆ JESD8-7 (1.65 V to 1.95 V)

◆ JESD8-5 (2.3 V to 2.7 V)

◆ JESD8-B/JESD36 (2.7 V to 3.6 V)

■ ESD protection:

◆ HBM JESD22-A114E exceeds 2000 V

◆ MM JESD22-A115-A exceeds 200 V

■ ±24 mA output drive (V_CC= 3.0 V)

■ CMOS low power consumption

■ Latch-up performance exceeds 250 mA

■ Direct interface with TTL levels

■ Inputs accept voltages up to 5 V

■ Multiple package options

■ Speciﬁed from −40 °C to +85 °C and −40 °C to +125 °C.

12 3 4 5 6 7...15

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