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74LVC06APW PDF预览

74LVC06APW

更新时间: 2024-11-06 11:12:03
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路触发器
页数 文件大小 规格书
12页 230K
描述
Hex inverter with open-drain outputsProduction

74LVC06APW 数据手册

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74LVC06A  
Hex inverter with open-drain outputs  
Rev. 7 — 4 August 2020  
Product data sheet  
1. General description  
The 74LVC06A provides six inverting buffers. The outputs are open-drain and can be connected to  
other open-drain outputs to implement active-LOW wired-OR or active-HIGH wired-AND functions.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices  
as translators in mixed 3.3 V and 5 V applications.  
2. Features and benefits  
5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 5.5 V  
CMOS low power consumption  
Direct interface with TTL levels  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-B exceeds 200 V  
CDM JESD22-C101E exceeds 1000 V  
Specified from -40 °C to +85 °C and -40 °C to +125 °C  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC06AD  
74LVC06APW  
74LVC06ABQ  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
TSSOP14  
plastic thin shrink small outline package; 14 leads; SOT402-1  
body width 4.4 mm  
DHVQFN14 plastic dual in-line compatible thermal enhanced  
very thin quad flat package; no leads; 14 terminals;  
body 2.5 × 3 × 0.85 mm  
SOT762-1  
 
 
 

74LVC06APW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVC06APWR TI

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