5秒后页面跳转
74LVC07APW-Q100 PDF预览

74LVC07APW-Q100

更新时间: 2024-11-10 02:56:59
品牌 Logo 应用领域
安世 - NEXPERIA 光电二极管逻辑集成电路
页数 文件大小 规格书
13页 227K
描述
Hex buffer with open-drain outputs

74LVC07APW-Q100 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:TSSOP,Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.69
系列:LVC/LCX/ZJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
逻辑集成电路类型:BUFFER湿度敏感等级:1
功能数量:6输入次数:1
端子数量:14最高工作温度:125 °C
最低工作温度:-40 °C输出特性:OPEN-DRAIN
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):260传播延迟(tpd):6.5 ns
筛选级别:AEC-Q100座面最大高度:1.1 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):1.2 V
标称供电电压 (Vsup):1.8 V表面贴装:YES
技术:CMOS温度等级:AUTOMOTIVE
端子面层:Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:4.4 mm

74LVC07APW-Q100 数据手册

 浏览型号74LVC07APW-Q100的Datasheet PDF文件第2页浏览型号74LVC07APW-Q100的Datasheet PDF文件第3页浏览型号74LVC07APW-Q100的Datasheet PDF文件第4页浏览型号74LVC07APW-Q100的Datasheet PDF文件第5页浏览型号74LVC07APW-Q100的Datasheet PDF文件第6页浏览型号74LVC07APW-Q100的Datasheet PDF文件第7页 
74LVC07A-Q100  
Hex buffer with open-drain outputs  
Rev. 2 — 14 December 2018  
Product data sheet  
1. General description  
The 74LVC07A-Q100 provides six non-inverting buffers. The outputs are open-drain and can  
be connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH  
wired-AND functions.  
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices  
as translators in mixed 3.3 V and 5 V applications.  
This product has been qualified to the Automotive Electronics Council (AEC) standard Q100  
(Grade 1) and is suitable for use in automotive applications.  
2. Features and benefits  
Automotive product qualification in accordance with AEC-Q100 (Grade 1)  
Specified from -40 °C to +85 °C and from -40 °C to +125 °C  
5 V tolerant inputs and outputs (open-drain) for interfacing with 5 V logic  
Wide supply voltage range from 1.2 V to 5.5 V  
CMOS low power consumption  
Direct interface with TTL levels  
Inputs accept voltages up to 5 V  
Complies with JEDEC standard:  
JESD8-7A (1.65 V to 1.95 V)  
JESD8-5A (2.3 V to 2.7 V)  
JESD8-C/JESD36 (2.7 V to 3.6 V)  
ESD protection:  
MIL-STD-883, method 3015 exceeds 2000 V  
HBM JESD22-A114F exceeds 2000 V  
MM JESD22-A115-A exceeds 200 V (C = 200 pF; R = 0 Ω)  
3. Ordering information  
Table 1. Ordering information  
Type number  
Package  
Temperature range Name  
Description  
Version  
74LVC07AD-Q100  
74LVC07APW-Q100  
74LVC07ABQ-Q100  
-40 °C to +125 °C  
-40 °C to +125 °C  
-40 °C to +125 °C  
SO14  
plastic small outline package; 14 leads;  
body width 3.9 mm  
SOT108-1  
TSSOP14  
plastic thin small outline package; 14 leads;  
body width 4.4 mm  
SOT402-1  
SOT762-1  
DHVQFN14 plastic dual in-line compatible thermal  
enhanced very thin quad flat package;  
no leads; 14 terminals; body 2.5 x 3 x 0.85 mm  
 
 
 

与74LVC07APW-Q100相关器件

型号 品牌 获取价格 描述 数据表
74LVC07APW-T NXP

获取价格

Hex buffer with open-drain outputs
74LVC07A-Q100 NEXPERIA

获取价格

Hex buffer with open-drain outputs
74LVC07AS14 DIODES

获取价格

HEX BUFFERS WITH OPEN DRAIN OUTPUTS
74LVC07AS14-13 DIODES

获取价格

HEX BUFFERS WITH OPEN DRAIN OUTPUTS
74LVC07AT14 DIODES

获取价格

HEX BUFFERS WITH OPEN DRAIN OUTPUTS
74LVC07AT14-13 DIODES

获取价格

HEX BUFFERS WITH OPEN DRAIN OUTPUTS
74LVC08A STMICROELECTRONICS

获取价格

LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE HIGH PERFORMANCE
74LVC08A NXP

获取价格

Quad 2-input AND gate
74LVC08A DIODES

获取价格

QUADRUPLE 2-INPUT AND GATES
74LVC08A ONSEMI

获取价格

Low-Voltage CMOS Quad 2-Input NAND Gate