Datasheet > 74LVC08A_04

74LVC08A_04

更新时间： 2024-11-09 04:47:47

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		输入元件
页数	文件大小	规格书
11页	259K
描述
LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE HIGH PERFORMANCE

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74LVC08A_04 数据手册

74LVC08A

LOW VOLTAGE CMOS QUAD 2-INPUT AND GATE

HIGH PERFORMANCE

■

5V TOLERANT INPUTS

HIGH SPEED: t = 4.1ns (MAX.) at V = 3V

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

■

SYMMETRICAL OUTPUT IMPEDANCE:

|I | = I = 24mA (MIN) at V = 3V

SOP

TSSOP

■

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

Table 1: Order Codes

PACKAGE

PLH

PHL

■

OPERATING VOLTAGE RANGE:

(OPR) = 1.65V to 3.6V (1.2V Data

T & R

SOP

74LVC08AMTR

74LVC08ATTR

Retention)

TSSOP

■

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 08

LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

operations and low power and low noise

applications.

It can be interfaced to 5V signal environment for

inputs in mixed 3.3/5V system.

It has more speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

DESCRIPTION

The 74LVC08A is a low voltage CMOS QUAD

2-INPUT AND GATE fabricated with sub-micron

silicon gate and double-layer metal wiring C MOS

technology. It is ideal for 1.65 to 3.6 V

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 4

1/11

July 2004

12 3 4 5 6 7...11

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