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74LS74APCQR PDF预览

74LS74APCQR

更新时间: 2024-11-17 13:00:35
品牌 Logo 应用领域
飞兆/仙童 - FAIRCHILD 触发器
页数 文件大小 规格书
6页 70K
描述
D Flip-Flop, 2-Func, Positive Edge Triggered, TTL, PDIP14,

74LS74APCQR 技术参数

是否Rohs认证:不符合生命周期:Obsolete
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.83Is Samacsys:N
JESD-30 代码:R-PDIP-T14JESD-609代码:e0
逻辑集成电路类型:D FLIP-FLOP功能数量:2
端子数量:14最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP14,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
子类别:FF/Latches标称供电电压 (Vsup):5 V
表面贴装:NO技术:TTL
温度等级:COMMERCIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGEBase Number Matches:1

74LS74APCQR 数据手册

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August 1986  
Revised March 2000  
DM74LS74A  
Dual Positive-Edge-Triggered D Flip-Flops with  
Preset, Clear and Complementary Outputs  
General Description  
This device contains two independent positive-edge-trig-  
gered D flip-flops with complementary outputs. The infor-  
mation on the D input is accepted by the flip-flops on the  
positive going edge of the clock pulse. The triggering  
occurs at a voltage level and is not directly related to the  
transition time of the rising edge of the clock. The data on  
the D input may be changed while the clock is LOW or  
HIGH without affecting the outputs as long as the data  
setup and hold times are not violated. A low logic level on  
the preset or clear inputs will set or reset the outputs  
regardless of the logic levels of the other inputs.  
Ordering Code:  
Order Number Package Number  
Package Description  
DM74LS74AM  
DM74LS85ASJ  
DM74LS74AN  
M14A  
M14D  
N14A  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide  
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.  
Connection Diagram  
Function Table  
Inputs  
Outputs  
PR  
L
CLR  
CLK  
X
D
X
X
X
H
L
Q
H
L
Q
L
H
L
H
L
X
H
L
X
H (Note 1) H (Note 1)  
H
H
H
H
H
H
H
L
L
H
L
X
Q0  
Q0  
H = HIGH Logic Level  
X = Either LOW or HIGH Logic Level  
L = LOW Logic Level  
↑ = Positive-going Transition  
Q
= The output logic level of Q before the indicated input conditions were  
0
established.  
Note 1: This configuration is nonstable; that is, it will not persist when either  
the preset and/or clear inputs return to their inactive (HIGH) level.  
© 2000 Fairchild Semiconductor Corporation  
DS006373  
www.fairchildsemi.com  

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