Datasheet > 74LS75

74LS75

更新时间： 2022-12-12 21:43:23

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		/
页数	文件大小	规格书
4页	103K
描述
4-BIT D LATCH

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数据手册

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74LS75 数据手册

SN54/74LS75

SN54/74LS77

4-BIT D LATCH

The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem-

porary storage for binary information between processing units and input/out-

put or indicator units. Information present at a data (D) input is transferred to

the Q output when the Enable is HIGH and the Q output will follow the data

input as long as the Enable remains HIGH. When the Enable goes LOW, the

information (that was present at the data input at the time the transition oc-

curred) is retained at the Q output until the Enable is permitted to go HIGH.

The SN54/74LS75 features complementary Q and Q output from a 4-bit

latch and is available in the 16-pin packages. For higher component density

applications the SN54/74LS77 4-bit latch is available in the 14-pin package

with Q outputs omitted.

4-BIT D LATCH

LOW POWER SCHOTTKY

CONNECTION DIAGRAMS DIP (TOP VIEW)

J SUFFIX

CERAMIC

CASE 620-09

GND

0–1

SN54/74LS75

N SUFFIX

PLASTIC

CASE 648-08

2–3

GND

0–1

D SUFFIX

SOIC

CASE 751B-03

SN54/74LS77

J SUFFIX

CERAMIC

CASE 632-08

2–3

PIN NAMES

LOADING (Note a)

HIGH

LOW

N SUFFIX

PLASTIC

CASE 646-06

D –D

Data Inputs

0.5 U.L.

2.0 U.L.

10 U.L.

0.25 U.L.

1.0 U.L.

5 (2.5) U.L.

Q –Q

Enable Input Latches 0, 1

Enable Input Latches 2, 3

Latch Outputs (Note b)

0–1

2–3

Q –Q

Complimentary Latch Outputs (Note b)

NOTES:

a) 1 Unit Load (U.L.) = 40 µA HIGH.

b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

Temperature Ranges.

D SUFFIX

SOIC

CASE 751A-02

TRUTH TABLE

(Each latch)

ORDERING INFORMATION

NOTES:

= bit time before enable

n+1

SN54LSXXJ

SN74LSXXN

SN74LSXXD

Ceramic

Plastic

SOIC

negative-going transition

= bit time after enable

n+1

negative-going transition

FAST AND LS TTL DATA

5-75

12 3 4

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与74LS75相关器件

型号	品牌	描述	获取价格	数据表
74LS75B	NXP	IC LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16, FF/Latch	获取价格
74LS75F	NXP	LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16	获取价格
74LS75N	RAYTHEON	D Latch, 1-Func, 4-Bit, TTL, PDIP16,	获取价格
74LS75NA+2	RAYTHEON	D Latch, 1-Func, 4-Bit, TTL, PDIP16,	获取价格
74LS76	HITACHI	Dual J-K Flip-Flop(with Preset and Clear)	获取价格
74LS76	ONSEMI	LOW POWER SCHOTTKY	获取价格