Datasheet > 74LS75

74LS75

更新时间： 2022-12-12 21:43:23

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		/
页数	文件大小	规格书
5页	53K
描述
Quad Latch

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数据手册

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74LS75 数据手册

August 1986

Revised March 2000

DM74LS75

Quad Latch

General Description

These latches are ideally suited for use as temporary stor-

age for binary information between processing units and

input/output or indicator units. Information present at a data

(D) input is transferred to the Q output when the enable is

HIGH, and the Q output will follow the data input as long as

the enable remains HIGH. When the enable goes LOW, the

information (that was present at the data input at the time

the transition occurred) is retained at the Q output until the

enable is permitted to go HIGH.

These latches feature complementary Q and Q outputs

from a 4-bit latch, and are available in 16-pin packages.

Ordering Code:

Order Number Package Number

Package Description

DM74LS75M

DM74LS75N

M16A

N16E

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Logic Diagram

Connection Diagram

(Each Latch)

Function Table (Each Latch)

Inputs

Enable

Outputs

Q₀

H = HIGH Level

L = LOW Level

X = Don't Care

= The Level of Q Before the HIGH-to-LOW Transition of ENABLE

DS006374

www.fairchildsemi.com

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与74LS75相关器件

型号	品牌	描述	获取价格	数据表
74LS75B	NXP	IC LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, PDIP16, FF/Latch	获取价格
74LS75F	NXP	LS SERIES, DUAL HIGH LEVEL TRIGGERED D LATCH, COMPLEMENTARY OUTPUT, CDIP16	获取价格
74LS75N	RAYTHEON	D Latch, 1-Func, 4-Bit, TTL, PDIP16,	获取价格
74LS75NA+2	RAYTHEON	D Latch, 1-Func, 4-Bit, TTL, PDIP16,	获取价格
74LS76	HITACHI	Dual J-K Flip-Flop(with Preset and Clear)	获取价格
74LS76	ONSEMI	LOW POWER SCHOTTKY	获取价格