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74LCX16374ATTR PDF预览

74LCX16374ATTR

更新时间: 2024-01-09 04:56:02
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意法半导体 - STMICROELECTRONICS 触发器输出元件输入元件
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74LCX16374ATTR 数据手册

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74LCX16374  
LOW VOLTAGE CMOS 16-BIT D-TYPE FLIP-FLOP (3-STATE)  
WITH 5V TOLERANT INPUTS AND OUTPUTS  
5V TOLERANT INPUTS AND OUTPUTS  
HIGH SPEED :  
f
= 150MHz (MIN.) at V = 3V  
MAX  
CC  
POWER DOWN PROTECTION ON INPUTS  
AND OUTPUTS  
SYMMETRICAL OUTPUT IMPEDANCE:  
TSSOP  
TUBE  
|I | = I = 24mA (MIN) at V = 3V  
PCI BUS LEVELS GUARANTEED AT 24 mA  
BALANCED PROPAGATION DELAYS:  
OH  
OL  
CC  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
OPERATING VOLTAGE RANGE:  
(OPR) = 2.0V to 3.6V (1.5V Data  
T & R  
V
CC  
TSSOP  
74LCX16374TTR  
Retention)  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 16374  
LATCH-UP PERFORMANCE EXCEEDS  
500mA (JESD 17)  
PIN CONNECTION  
ESD PERFORMANCE:  
HBM > 2000V (MIL STD 883 method 3015);  
MM > 200V  
DESCRIPTION  
The 74LCX16374 is a low voltage CMOS 16 BIT  
D-TYPE FLIP-FLOP with 3 STATE OUTPUTS  
NON INVERTING fabricated with sub-micron  
2
silicon gate and double-layer metal wiring C MOS  
technology. It is ideal for low power and high  
speed 3.3V applications; it can be interfaced to 5V  
signal environment for both inputs and outputs.  
These 16 bit D-TYPE flip-flops are controlled by  
two clock inputs (nCK) and two output enable in-  
puts(nOE). On the positive transition of the (nCK),  
the nQ outputs will be set to the logic state that  
were setup at the nD inputs. While the (nOE) input  
is low, the 8 outputs (nQ) will be in a normal state  
(high or low logic level) and while high level the  
outputs will be in a high impedance state.  
Any output control does not affect the internal op-  
eration of flip flops; that is, the old data can be re-  
tained or the new data can be entered even while  
the outputs are off.  
It has same speed performance at 3.3V than 5V  
AC/ACT family, combined with a lower power  
consumption.  
All inputs and outputs are equipped with protec-  
tion circuits against static discharge, giving them  
2KV ESD immunity and transient excess voltage.  
February 2003  
1/10  

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