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74LCX126SJX PDF预览

74LCX126SJX

更新时间: 2024-11-03 23:24:19
品牌 Logo 应用领域
其他 - ETC 驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 97K
描述
4-Bit Buffer/Driver

74LCX126SJX 数据手册

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September 2000  
Revised September 2000  
74LCX126  
Low Voltage Quad Buffer  
with 5V Tolerant Inputs and Outputs  
General Description  
Features  
5V tolerant inputs and outputs  
The LCX126 contains four independent non-inverting buff-  
ers with 3-STATE outputs. Each output is disabled when  
the associated output-enable (OE) input is LOW. The  
inputs tolerate voltages up to 7V allowing the interface of  
5V systems to 3V systems.  
2.3V–3.6V VCC specifications provided  
5.5 ns tPD max (VCC = 3.3V), 10 µA ICC max  
Power down high impedance inputs and outputs  
Supports live insertion/withdrawal (Note 1)  
±24 mA output drive (VCC = 3.0V)  
The 74LCX126 is fabricated with an advanced CMOS tech-  
nology to achieve high speed operation while maintaining  
CMOS low power dissipation.  
Implements patented noise/EMI reduction circuitry  
Latch-up performance exceeds 500 mA  
ESD performance:  
Human body model > 2000V  
Machine model > 100V  
Note 1: To ensure the high-impedance state during power up or down, OE  
should be tied to GND through a pull-up resistor: the minimum value or the  
resistor is determined by the current-sourcing capability of the driver.  
Ordering Code:  
Order Number Package Number  
Package Description  
74LCX126M  
M14A  
M14D  
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150Narrow  
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
74LCX126SJ  
74LCX126MTC  
MTC14  
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.  
Logic Symbol  
Connection Diagram  
IEEE/IEC  
Truth Table  
Pin Descriptions  
Inputs  
Output  
On  
Pin Names  
Description  
Inputs  
OEn  
An  
An  
H
H
L
L
H
X
L
H
Z
OEn  
Output Enable Inputs  
Outputs  
On  
H = HIGH Voltage Level  
L = LOW Voltage Level  
Z = High Impedance  
X = Immaterial  
© 2000 Fairchild Semiconductor Corporation  
DS500386  
www.fairchildsemi.com  

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