74LCX139

更新时间： 2024-11-03 22:40:23

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		解码器解复用器
页数	文件大小	规格书
12页	283K
描述
LOW VOLTAGE CMOS DUAL 2 TO 4 DECODER/DEMULTIPLEXER

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74LCX139 数据手册

74LCX139

LOW VOLTAGE CMOS

DUAL 2 TO 4 DECODER/DEMULTIPLEXER

■

5V TOLERANT INPUTS

HIGH SPEED:

= 6.2ns (MAX.) at V = 3V

■

POWER DOWN PROTECTION ON INPUTS

AND OUTPUTS

SYMMETRICAL OUTPUT IMPEDANCE:

SOP

TSSOP

|I | = I = 24mA (MIN) at V = 3V

■

PCI BUS LEVELS GUARANTEED AT 24 mA

BALANCED PROPAGATION DELAYS:

Table 1: Order Codes

PACKAGE

PHL

PLH

■

OPERATING VOLTAGE RANGE:

(OPR) = 2.0V to 3.6V (1.5V Data

T & R

SOP

74LCX139MTR

74LCX139TTR

Retention)

TSSOP

■

PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 139

LATCH-UP PERFORMANCE EXCEEDS

500mA (JESD 17)

ESD PERFORMANCE:

HBM > 2000V (MIL STD 883 method 3015);

MM > 200V

The active low enable input can be used for gating

or as a data input for demultiplexing applications.

While the enable input is held high, all four outputs

are high independently of the other inputs.

It has same speed performance at 3.3V than 5V

AC/ACT family, combined with a lower power

consumption.

DESCRIPTION

All inputs and outputs are equipped with

protection circuits against static discharge, giving

them 2KV ESD immunity and transient excess

voltage.

The 74LCX139 is a low voltage CMOS DUAL 2

LINE DECODER/DEMULTIPLEXER

fabricated with sub-micron silicon gate and

double-layer metal wiring C MOS technology.

It is ideal for low power and high speed 3.3V

applications; it can be interfaced to 5V signal

environment for inputs.

Figure 1: Pin Connection And IEC Logic Symbols

Rev. 3

1/12

September 2004

12 3 4 5 6 7...12

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